16940 Perl Jobs - Page 2

- Expertise in ASIC physical design - Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR. - Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization. - Expertise in floor planning, methodology setup, and signoff processes for large IPs. - Expertise in scripting (TCL, Python, Perl) for design flow automation. - Drive SOC-level floor planning, partitioning, and die size estimation. - Manage hierarchical design flows, including block-level pin placement and HFN implementation. - Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree). - Provide technical mentorship to junior engineers and cross-functi...

- Expertise in ASIC physical design - Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR. - Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization. - Expertise in floor planning, methodology setup, and signoff processes for large IPs. - Expertise in scripting (TCL, Python, Perl) for design flow automation. - Drive SOC-level floor planning, partitioning, and die size estimation. - Manage hierarchical design flows, including block-level pin placement and HFN implementation. - Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree). - Provide technical mentorship to junior engineers and cross-functi...

- Expertise in ASIC physical design - Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR. - Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization. - Expertise in floor planning, methodology setup, and signoff processes for large IPs. - Expertise in scripting (TCL, Python, Perl) for design flow automation. - Drive SOC-level floor planning, partitioning, and die size estimation. - Manage hierarchical design flows, including block-level pin placement and HFN implementation. - Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree). - Provide technical mentorship to junior engineers and cross-functi...

- Expertise in ASIC physical design - Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR. - Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization. - Expertise in floor planning, methodology setup, and signoff processes for large IPs. - Expertise in scripting (TCL, Python, Perl) for design flow automation. - Drive SOC-level floor planning, partitioning, and die size estimation. - Manage hierarchical design flows, including block-level pin placement and HFN implementation. - Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree). - Provide technical mentorship to junior engineers and cross-functi...

Designation - MySql Database Administrator Experience -3 - 5 Years Job Location Bangalore Primary responsibilities: - • Installation and configuration of MySQL instances on single or multiple ports. • Hands-on experience of working with MySQL 8 and MySQL 5.7. • Clear understanding of MySQL Replication process flows, threads, setting up multi node clusters and basic troubleshooting. • Understanding of at least one of the backup and recovery methods for MySQL. • Strong fundamentals of SQL and able to understand and tune complex SQL queries when needed. • Strong fundamentals on the Linux system side and monitoring tools like top, iostats , sar etc. • At Least couple of years of production hands...

5 -10 years of hands-on experience with GoldenSource, preferably version 8.x Strong expertise in GoldenSource components including Workflows, Connectors, Business Rules, and GSOs Solid understanding of the GoldenSource data model Experience with Build and Packaging using Installation Center Proficient in Oracle 11g/12c databases Skilled in Shell, Perl, or Python scripting Familiarity with Java 1.7/1.8 ,Rest APIClear understanding of the Software Development Life Cycle (SDLC) Experience working in Agile methodology is a plus Proficient in code management tools such as SVN/Git Domain ExpertiseStrong knowledge of the Capital Markets domain Good understanding of Reference Data Soft Skills Strong...

Summit Techno Funtional Analyst will be responsible for providing the Analysis, documentation, Designing and developing Solution for the Regulatory and change projects. He is expected to manage the Business users/ Stake holders in terms of Project delivery. He should have good knowledge of SDLC and excellent Summit Development skills are required. Should be able to understand the Functional requirements provided by the Business Analyst and act as a point of contact for project in all the phases of SDLC. Main duties/responsibilities will include: Liaising with Business users in Gathering the requirements, Design and develop solution Work with the Business analyst in designing the solution to ...

About Position: We are looking for an experienced Performance tester to be responsible for providing solutions for technical issues which may affect product delivery. You will facilitate requirement analyses, conduct peer reviews, and provide feedback, and enhance frameworks. To be successful as a Tester, you should demonstrate sound knowledge of industry best practices, good organisational and leadership skills, and proficiency in Performance testing technologies. Ultimately, as a top-notch, you should have good analytical skills, the ability to anticipate issues and frame remedial actions, and excellent teamwork skills. Role: QA Lead-Performance Testing Location: Bangalore Experience: 6 to...

Job Summary Come Join Our Software Integration Team!!Our main activity consists in setting up GE Vernova software in different environments for internal and external customers, supporting project activities and providing expertise in tailoring the components based on requirements. We have a hybrid work environment as we work from home, the office and travel to customer sites as needed.The integration engineer is a key member in all projects, being engaged throughout the full lifecycle (Development, Factory Acceptance Tests, Site Acceptance Tests, Cutover, Support). GE Vernova allows us to bring a significant contribution to the Worldwide Electrical Energy context. Delivering on life-critical...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Title: Wireless RD IP Design Lead Location: Bangalore Roles and Responsibilities Contribute to flagship Wireless IP development covering WAN, WLAN, GNSS, and Bluetooth technologies. Define and develop next-generation Wireless RD products. Work on front-end RTL design for wireless IP or DSP-based IPs. Develop micro-architecture and RTL coding using System Verilog , Verilog , or VHDL . Provide technical leadership across design activities, ensuring best practices and innovation. Mentor and guide team members on architecture, RTL design, and verification strategies. Coordinate with cross-functional teams ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what''s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performan...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what''s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performan...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Title: Wireless RD IP Design Specialist Location: Bangalore Roles and Responsibilities Contribute to flagship Wireless IP development covering WAN, WLAN, GNSS, and Bluetooth technologies. Define and develop next-generation Wireless RD products. Work on front-end RTL design for wireless IP or DSP-based IPs. Develop micro-architecture and RTL coding using System Verilog , Verilog , or VHDL . Collaborate with multi-geo teams for design and verification. Technical Requirements Strong experience in IP design (preferably wireless/DSP domain). Exposure to synthesis and Static Timing Analysis (STA). Awareness ...

About Groww We are a passionate group of people focused on making financial services accessible to every Indian through a multi-product platform. Each day, we help millions of customers take charge of their financial journey. Customer obsession is in our DNA. Every product, every design, every algorithm down to the tiniest detail is executed keeping the customers’ needs and convenience in mind. Our people are our greatest strength. Everyone at Groww is driven by ownership, customer-centricity, integrity and the passion to constantly challenge the status quo. Are you as passionate about defying conventions and creating something extraordinary as we are? Let’s chat. Our Vision Every individual...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Description Summary We are looking for Engineers with strong PHY Layer experience to implement Signal Processing Algorithms for WLAN Communication Systems .This individual will work independently under supervision to deliver on the Implementation, Validation and demonstration of the PHY Layer Calibration Algorithms.This individual is also needed to interface with other teams as part of the role for delivering the complete system solution. Skills/Requirements: - Design understanding and/or experience on Modem PHY layer, understanding of RF impairments , and good signal-processing coding skills.- Solid b...

Job Area: Engineering Group, Engineering Group > Systems Test Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what''s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software s...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what''s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor''s degree in Compute...

General Summary: Job Title: Wireless R&D IP Design Specialist Location: Bangalore Roles and Responsibilities Contribute to flagship Wireless IP development covering WAN, WLAN, GNSS, and Bluetooth technologies. Define and develop next-generation Wireless R&D products. Work on front-end RTL design for wireless IP or DSP-based IPs. Develop micro-architecture and RTL coding using System Verilog , Verilog , or VHDL . Collaborate with multi-geo teams for design and verification. Technical Requirements Strong experience in IP design (preferably wireless/DSP domain). Exposure to synthesis and Static Timing Analysis (STA). Awareness of low-power and high-speed design techniques. Familiarity with indu...

Experience in Android and Linux Multimedia frameworks and Linux Kernel development with a focus on V4L2. Experience in Java/perl/python programming. Knowledge of software design patterns and multi-threaded programming. Knowledge of computer architecture, operating systems, data structures, and basic algorithms, particularly with respect to Linux/Android platforms. Software debugging skills in embedded real time operating systems, preferably on Linux platforms Additional experience in one or more of the following areas: Video usage models including playback, streaming, camcorder, WiFi display, and content protection Video compression standards (e.g. H264/H.265/AV1) Streaming protocols and imp...

Design Verification and RTL/GLS debug Regression Run , Assertion and Coverage Closure activities Need to be good in SV/UVM Experience (years) : 3+ years Education Qualification: BE/ME

General Summary: Verification & Validation team is currently looking for self-motivated engineers who will perform Audio Verification including system level Verification and debug. The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Ver...

You will be part of ACE India , in the P- Core design team driving Intel''s latest CPU''s in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems. Your responsibilities will include but not limited to: Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area. In depth understanding of different memory design concepts ((SRAM/RF/ROM). Expertise in Static timing analysis concepts. Close work with Layout and Floor planning teams. Back-end design implementation of new features. Expertise in Mem...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what''s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor''s degree in Compute...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what''s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor''s degree in Compute...

- Expertise in ASIC physical design - Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR. - Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization. - Expertise in floor planning, methodology setup, and signoff processes for large IPs. - Expertise in scripting (TCL, Python, Perl) for design flow automation. - Drive SOC-level floor planning, partitioning, and die size estimation. - Manage hierarchical design flows, including block-level pin placement and HFN implementation. - Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree). - Provide technical mentorship to junior engineers and cross-functi...