MTS SILICON DESIGN ENGINEER ( SOC Low Power-RTL lead)

THE ROLE:

As a member of the Client Group, you will help bring to life cutting-edge designs.?As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

The Person:

• If you have a knack for power saving techniques, including clock gating and UPF-based power gating, this role is for you. You will be responsible for generating Power spec, UPF, performing quality checks of power-gated digital designs,execute the SoC RTL integrationand working collaboratively with the IP team.

Key Responsibilities:

• Understanding of IP/SS/SoC Power Management(PM) techniques.
• Converting PM Specification to UPF
• Perform low power quality checks VSI/VCLP
• Debugging experience on Power aware simulation (NLP sim)
• Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
• Work in partnership with SOC teams to support the IP at SOC level, including UPF, verification, Power sequence, and post-silicon bring-up
• Need to understand clocking, reset and soc top level topology changes to make connectivity as per the topology across Ips.
• Need to understand the requirements of power domain(power architecture) to write UPFs.
• Collaborate with architects, DV and PD engineers to understand the new features to group the logic into tiles based on functionality as well as PD FP requirements.
• Must have been expert with RTL coding and other Debug capabilities.

Preferred Experience:

• 7+ years full-time experience in IP/SOC hardware design
• Experience doing ECOs
• Experience with power aware CDC runs
• Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
• Experience with RTL Quality Checks - Verilog lint tools (Spyglass), verilog simulation tools (VCS) and Clock domain crossing (CDC) tools
• Proficient in IP level ASIC or SoC level RTL integration work and verification
• Good understanding and hands-on experience in the Timing, UPF, CDC, RDC and other quality check concepts
• Proficient in debugging RTL code using quality check and simulation tools.
• Outstanding interaction skills while communicating both written and verbally
• Ability to work with multi-level functional teams across various geographies
• Outstanding problem-solving and analytical skills
• Exposure to leadership or mentorship is an asset.

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering