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MTS SILICON DESIGN ENGINEER ( SOC Low Power-RTL lead) AMD

7.0 - 10.0 years

8 - 10 Lacs

Bengaluru, Karnataka, India

On-site

THE ROLE: As a member of the Client Group, you will help bring to life cutting-edge designs.?As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. The Person: If you have a knack for power saving techniques, including clock gating and UPF-based power gating, this role is for you. You will be responsible for generating Power spec, UPF, performing quality checks of power-gated digital designs,execute the SoC RTL integrationand working collaboratively with the IP team. Key Responsibilities: Understanding of IP/SS/SoC Power Management(PM) techniques. Convert...

Posted 3 months ago

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