Posted:22 hours ago|
Platform:
Work from Office
Full Time
Expertise in working on memory layout design for advanced nodes (TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability
Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustnessExpertise in performing debugging of silicon failures and identify layout-related issuesCreate detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom CompilerPerform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rulesWork closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA)Provide feedback on circuit designs to improve layout efficiencyUtilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits)Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL)Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit.
Location- Bengaluru, Taiwan,Beijing, Moscow, Romania
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