9 Jobs in Beijing

Expertise in ASIC or Digital physical design Expertise in RTL2GDSII physical design flows development (SNPS tool suite) Expertise in PD tool expertise (SNPS based - both construction & sign-off) Expertise in Cadence tools especially Innovus / Voltus Expertise in Python, Tcl, Shell programming skills Expertise in sign-off reports, triaging and root-cause analysis and suggest flow fixes Expertise in constraints / timing - STA. Expertise in full chip synthesis flow Expertise in PowerBI Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Moscow, Taiwan, Vietnam

Expertise in Digital Verification Expertise in Functional Verification Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim, Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath, DSP based ASICs Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit. Location - Bangalore, Beijing, Dallas, Romania, Taiwan

Expertise in working on memory layout design for advanced nodes (TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness Expertise in performing debugging of silicon failures and identify layout-related issues Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA) Provide feedback on circuit designs to improve layout efficiency Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits) Automate repetitive tasks and improve workflow efficiency using scripting (eg Python, SKILL) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Moscow, Romania, Taiwan

Expertise in working on memory layout design for advanced nodes (TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness Expertise in performing debugging of silicon failures and identify layout-related issues Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA) Provide feedback on circuit designs to improve layout efficiency Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits) Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit. Location- Bengaluru, Taiwan,Beijing, Moscow, Romania

Expertise in ASIC or Digital physical design Expertise in RTL2GDSII physical design flows development (SNPS tool suite) Expertise in PD tool expertise (SNPS based - both construction & sign-off) Expertise in Cadence tools especially Innovus / Voltus Expertise in Python, Tcl , Shell programming skills Expertise in sign-off reports, triaging and root-cause analysis and suggest flow fixes Expertise in constraints / timing - STA. Expertise in full chip synthesis flow Expertise in PowerBI Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Moscow, Taiwan, Vietnam

Expertise in Digital Verification Expertise in Functional Verification Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim, Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath, DSP based ASICs Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit. Location - Bangalore, Beijing, Dallas, Romania, Taiwan

Expertise in Electrical Bench Characterization Expertise in Electrical performance validation: PCIe Gen5, LP / DDR4 / 5, Ethernet (10G/25G) Expertise in BERTs, VNAs, Oscilloscopes, Signal Integrity Expertise in debugging silicon / platform issue Expertise in data analysis / statistics Expertise in Test scripting (LabVIEW / Python preferred) Expertise in test automation Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit.

Expertise in Platform / Board design (Schematics / Layout) Expertise in using Lab tools: Oscilloscope, Multimeter, Analyzers, simple rework Expertise in cross-functional team interaction (Firmware / BIOS / Layout / IP / Silicon) Expertise in validation: RAS (DDR ECC, Ethernet IPs, PCIe), interfaces (I2S, I2C, USB, SATA, SSD, NVMe) Expertise in debugging using Logic Analyzer, Protocol Analyzers Expertise in SOC / Platform bring-up, failure debug Expertise in Scripting : Python, Ruby, or PERL Expertise in x86 architecture, LPDDR3/4, DDR4, USB, eMMC, PCIe, NVMe, SPI, UART, I2C Expertise in Graphics/Video: GPU, Codecs, Display: DP, HDMI, DVIExpert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit ,

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node 180 nm is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Taiwan, Vietnam