As an experienced Layout Memory Engineer, your role will involve hands-on experience with important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. You should have a strong background in working with 16nm/14nm/10nm/7nm/Finfet process technologies and top-level memory integration, along with expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. Your responsibilities will also include addressing IR/EM related issues in memory layouts and utilizing Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A solid understanding of ultra-deep sub-micron layout design challenges and DFM guidelines is crucial for this role. Additionally, experience or a strong interest in memory compilers will be beneficial. You will be expected to be an excellent team player, collaborating effectively with external customers and cross-functional teams. Qualifications Required: - Masters Degree in Electronic/Electrical Engineering with a Major in VLSI/Microelectronics Location: Bangalore Experience: 3+ Years & Above Number of Positions: 3,

More Jobs at Pozibility Technologies

Memory Layout Design Engineer

karnataka

3.0 - 7.0 yrs

Salary: Not disclosed

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Memory Layout Design Engineer