8 Gpu Architecture Jobs

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 3 to 12 years of experience or a master's degree in electrical engineering or computer engineering. 6+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content. Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Act as focal point between design and tool vendors for issues and feature enhancements. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure Monitoring and improve existing simulation environments and simulation efficiency. Experience with Performance Validation of GPUs and automation framework using Python is desirable

We are looking for exceptionally smart people who believe that AI will change the world and would like to join our exciting journey. https://habana.ai/Will be responsible for presilicon modeling of AI hardware accelerator architecture. Will also be responsible for enabling AI software stack on simulation models. Opportunity to learn and contribute to complete AI software stack and future GPU/AI architecture. Qualifications Computer Science Software focused graduates with can-do attitude. This is for 2-7 years' experience range. Strong C++ programming skills, computer architecture knowledge, and preferably python knowledge. Experience and knowledge of SystemC, or architecture simulation models or pre-silicon virtual platform development, or GPU architecture is a plus. We're working on Intel Gaudi AI accelerators, and AI GPUs in niche domain of simulating super-complex architecture for hardware-software co-design. No AI / ML experience required, only strong Computer Science fundamentals. The team excels in diversity, innovation, and technical leadership.

Intel Habana AI group focuses on developing disruptive solutions that will shape the future of AI and Deep Learning computing. Led by top technologists and successful entrepreneurs, our vision is to take AI processing from its current limits to the peak of its potential. We see challenges as a tremendous opportunity, we are focused on execution and determined to make our vision come true. We are looking for exceptionally smart people who believe that AI will change the world and would like to join our exciting journey. https://habana.ai/Will be responsible for presilicon modeling of AI hardware accelerator architecture. Will also be responsible for enabling AI software stack on simulation models. Opportunity to learn and contribute to complete AI software stack and future GPU/AI architecture. Qualifications Computer Science Software focused graduates with can-do attitude. This is for 2-7 years' experience range. Strong C++ programming skills, computer architecture knowledge, and preferably python knowledge. Experience and knowledge of SystemC, or architecture simulation models or pre-silicon virtual platform development, or GPU architecture is a plus. We're working on Intel Gaudi AI accelerators, and AI GPUs in niche domain of simulating super-complex architecture for hardware-software co-design. No AI / ML experience required, only strong Computer Science fundamentals. The team excels in diversity, innovation, and technical leadership. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 3 to 12 years of experience or a master's degree in electrical engineering or computer engineering. 6+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content. Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Act as focal point between design and tool vendors for issues and feature enhancements. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure Monitoring and improve existing simulation environments and simulation efficiency. Experience with Performance Validation of GPUs and automation framework using Python is desirable

Intel's Graphic solutions are used by millions of people every day, changing the way the world sees in unprecedented ways. The Graphics IP team responsible for providing the next gen Graphics and High-Performance Compute IP's which go into SoC's in all of Intel Graphics IP products - Integrated, Discrete and Data Centre AI products. We strive to lead the industry through continuous innovation and world-class engineering. We are looking for Experienced Pre-Silicon RTL Design and Verification engineers, where you will work closely with architects/micro-arch's, structural design, and many simulator experts. If you have the desire and ability to learn quickly and gain new knowledge your potential here is limitless. With exciting work and by being at the at the very center of IP designing and validation and working alongside some of the best engineers in the industry, great learning is assured. Qualifications Bachelor / Masters degree in Electronics or Computer Engineering with 3-10 years experience in silicon design development. Well versed with Verilog / System Verilog / UVM. Experience in Pre-silicon verification, Testplan, testbench, Coverage/Assertion writing and closure. Exposure to CPU or GPU Architecture (Computer Architecture Knowledge) Debug Experience with industry standard frontend design and verification flows, tools and methodology Programming / scripting languages like Python, Perl, or Shell scripting automation methods. Good verbal/written communication skills. Effective team player with continuous learning mindset.Be willing to balance multiple tasks. Prior experience in IP development teams would be an added advantage. Experience in IP coverage and functional verification.

Key Responsibilities: Design, develop, and maintain display drivers for various operating systems and hardware platforms, including open WFDB. Work on integrating display drivers with GPU and operating system graphics stacks, including MIPI DSI, DP port, and other relevant interfaces. Optimization and Debugging: Optimize display drivers for performance, power consumption, and memory usage. Debug and resolve issues related to display driver performance and functionality, using tools like SurfaceFlinger and HW Compositor. Qualifications: Bachelors or Masters degree in Computer Science, Electrical Engineering, or a related field. Proven experience in developing display drivers for GPUs and display controllers. Strong programming skills in C/C++. Experience with operating system graphics stacks (e.g., DirectX, OpenGL, Vulkan, etc.). Knowledge of display technologies and standards (e.g., HDMI, DisplayPort, MIPI DSI, etc.). Familiarity with hardware debugging tools and techniques, including SurfaceFlinger and HW Compositor. Excellent problem-solving and analytical skills. Strong communication and teamwork abilities. Preferred Qualifications: Experience with embedded systems and real-time operating systems (RTOS). Knowledge of Linux kernel and device drivers. Experience with GPU architecture and graphics rendering pipelines. Familiarity with Agile development methodologies.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 3 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 6+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Act as focal point between design and tool vendors for issues and feature enhancements. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure Monitoring and improve existing simulation environments and simulation efficiency. Experience with Performance Validation of GPUs and automation framework using Python is desirable

Exposure to Emulation model build and sanity bring-up Proven Emulation Testbench bring-up experience with C++ and SystemVerilog BFM models Expertise in porting C++/SystemVerilog Simulation Testbenches to Emulation Hands-on experience with SystemVerilog, C++ based testbenches BFM coding using C++ or SystemVerilog Strong Python scripting skills Exposure to GPU emulation model build and sanity bring-up Good understanding of GPU architecture Strong functional verification expertise