Design Verification Engineer

0 years

0 Lacs

Posted:5 days ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

  1. 7+ experience in verification with strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology
  2. Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI
  3. Solid understanding of digital hardware design and Verilog HDL.
  4. Detailed understanding and experience of the current verification strategies required for sophisticated SoC development, including software-based techniques
  5. Good knowledge of test plan creation and tracking
  6. Experience with Perl, Python or other scripting language

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