As a Senior Engineer, Package Design based in Milpitas, CA, you will primarily focus on signal and power integrities analyses and routing analyses of package substrates. You will report to the Director of Package Design in the USA and collaborate closely with the Package design team at our parent company's headquarters in Japan, as well as with the Marketing and Engineering teams based in Milpitas during the pre/post sales process. Your role will require a comprehensive understanding of package technology and design, particularly in areas such as high-performance build-up substrates, flip chip assembly, and 2.5D packaging. Proficiency in extracting/simulating package designs for Signal and Power integrities using tools like HFSS and/or ADS tools is crucial for this position. To qualify for this role, you should hold a Bachelor's degree in Electrical Engineering or a related semiconductor packaging discipline, with a preference for candidates with a Master's degree. You must have 8 to 10 years of experience in semiconductor packaging design, modeling, extraction, and simulations, along with a proven track record of success in a cross-functional team environment. Ideal candidates will possess hands-on experience in high-speed signal integrity and power integrity, package decoupling caps optimizations, PCB design, and routing analyses. Proficiency in high-speed Serdes, PCIe, LPDDR, and Ethernet technologies, as well as expertise in time domain analyses, jitter budgeting, and multi-physics electro-thermal analysis, will be advantageous. Additionally, familiarity with package manufacturing and assembly rules, chip and package reliability analyses, die+Pkg+pcb PDN model time and frequency, IR drop, and CPM die model using Redhawk are desirable skills for this role. Strong presentation and communication skills, the ability to work with Package Layout engineers, and a collaborative approach to problem-solving are also essential for success in this position.,
Job Title: Design Verification Engineer Location: Bangalore, India Type - Full time Description: Client is seeking a Design Verification Engineer. The role is technical, hands-on, in charge of the verification environment for new silicon projects and developments. We are looking for an experienced professional with Passion & Drive to succeed. Primary Responsibilities Include: Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practices. Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action. Overall, responsible for verification of ASIC designs To include such things as: Design Verification Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team. Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible for Debugging Designs for High throughput, Low Latency of Pipeline and Dynamic Power Management at full system level. Setup Verification Regression suites at RTL Level & Corresponding Netlist Level after Synthesis to test any/all Corner case conditions. Work closely with Socionext's design team to ensure the Company is meeting design requirements for projects. This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benches. Work closely with Socionext's Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timely and accurate deliverables with customers within schedules Necessary Qualifications: BS or MS in Computer Science or Electrical Engineering. 5-10+ years of industry experience bringing silicon ICs into high volume production. Must have strong experience with UVM. Must have a full chip verification experience Experience of leading a single project. Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshooting in Real Time. Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification) Expertise in writing Perl / Python, awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers. Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation Experience with low-level programming of systems in C/C++. Experienced in writing scripts in languages such as Perl, Python, and Tcl. Functional understanding of constrained random verification process, functional coverage, and code coverage. Low power verification UPF Team player with excellent communication skills and the desire to take on diverse challenges. Customer interaction Other Qualifications: Good knowledge of low power cameras and imaging systems is a plus Experience with formal verification tools is a plus. CPU Security, Secure boot, Secure JTAG Familiarity with ARM architecture Familiarity with scripting/programming with Perl/Python, Tcl, C/C++
As a Design Verification Engineer at our client's company, your role will be technical and hands-on, overseeing the verification environment for new silicon projects and developments. Your experience and drive to succeed will be key in this position. Key Responsibilities: - Manage all aspects of the verification methodology and ensure uniform standards and best practices are applied. - Collaborate with other Design Verification teams to identify and address any gaps in the verification flow. - Verify ASIC designs by implementing test benches in UVM and System Verilog, running regressions at RTL and gate level, reporting DV metrics, debugging failures, and providing feedback to the design team. - Oversee debugging problems and troubleshooting in real-time, focusing on high throughput, low latency of pipeline, and dynamic power management at the full system level. - Set up verification regression suites at RTL level and netlist level post-synthesis to test all corner case conditions. - Work closely with the design team to ensure project requirements are met, including reviewing specifications, understanding chip architecture, developing tests and coverage plans, and defining methodologies and test benches. - Collaborate with the Custom SoC department to provide excellent customer service, support timely deliverables, and drive accurate project outcomes. Qualifications Required: - BS or MS in Computer Science or Electrical Engineering. - 5-10+ years of industry experience in bringing silicon ICs into high volume production. - Strong experience with UVM and full chip verification. - Knowledge of ARMv8, interconnect, memory coherence, and memory architectures. - Familiarity with Formality and various verification tools. - Expertise in scripting languages like Perl, Python, awk, sed, and common scripts for automation. - Advanced knowledge of ASIC design and verification flow, including RTL design, simulation, test bench development, equivalence checking, timing analysis, and more. - Understanding of constrained random verification processes, functional coverage, and code coverage. - Experience with low-level programming in C/C++ and writing scripts in Perl, Python, and Tcl. - Team player with excellent communication skills and a proactive approach to challenges. Additional Details: - Good knowledge of low power cameras and imaging systems is a plus. - Experience with formal verification tools, CPU security, secure boot, and familiarity with ARM architecture will be advantageous in this role. In this role, you will play a critical part in the verification process of ASIC designs and collaborate with various teams to ensure successful project outcomes. Your expertise in verification methodologies and strong technical skills will contribute to the overall success of the company's projects.,