DESIGN and VERIFICATION Trainer

0 years

0 Lacs

Posted:3 days ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Role Description


Design and Verification Trainer


Required Skillsets


Strong knowledge of hardware description languages like Verilog/System Verilog

Proficiency in verification methodologies such as Universal Verification Methodology (UVM)/ SystemVerilog Assertions (SVA) is crucial 

Experience with simulation and debugging tools (e.g. Synopsys VCS/VERDI, Spyglass)

Proficiency in Scripting

Analytical and Problem Solving Skills


Qualifications

  • Master's degree in Electronics/VLSI Design (Preferable)
  • Curriculum Development expertise
  • Teaching and Instructional Design abilities
  • Training experience
  • Excellent communication and presentation skills
  • Experience in VLSI design or semiconductor industry
  • Design Thinking skills

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