90 Cache Jobs - Page 4

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas:instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role :: As a "CPU Core Validation Engineer" you would be part of CPU Validation team in CPU org working on validation of CPU core pipeline arch and micro arch features. Roles and Responsibilities: Develop detailed test plan considering the IP arch and uarch features. Work with CPU design and verification teams to develop CPU bring up and functional validation test plans for the IP owned. Develop validation methodology and test contents to exercise on emulators during pre-Si phase and on Silicon. Work with SOC bring up teams, software teams to plan CPU core features bringup and end to end validation. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist validation of CPU on silicon. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future CPU bringup"™s. Minimum Requirements: BA/BS degree in CS/EE with 5+ years"™ experience. 5+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools. Preferred Requirements: Good understanding of micro-processor architecture, in domains such as:Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management. Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness. Experience in writing Test plans and Assembly code. Ability to develop and work independently on a block/unit of the design Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Qualcomm Technologies Inc., the maker of the industry-leading Snapdragon SoCs, is the largest provider of complete chipset solutions for Microsoft Windows on Snapdragon products. Qualcomm is committed to developing solutions for the next generation of Windows on Snapdragon devices . The ideal software engineer will act as a key member of an Agile Scrum Team and play a pivotal role in the end-to-end lifecycle of all Windows-on-Snapdragon product lines. Strong software development skills that will allow you to act as a hands-on contributor to gather requirements, design, and develop improvements to the Windows-on-Snapdragon continuous integration build systems, software release process, and developer operations tools. Communication and collaboration skills are essential as part of this platform team as you will need to coordinate with internal and external teams to bring up, support, triage, and unblock issues on Qualcomm chipsets Minimum Qualifications: "¢ Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. "¢ 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. . We are seeking a highly skilled Full-Stack developer with expertise in Python and C#. The ideal candidate will have a strong background in both front-end and back-end development, a history of delivering high-quality software solutions, and the ability to be a key contributor to a team developing features and technical solutions. The Ideal Candidate will have:"¢ Design, develop, test, and maintain web applications using Python and C#. "¢ Implement front-end interfaces using ASP.net, HTML, CSS, and JavaScript "¢ Design and maintain SQL databases, and write efficient SQL queries. "¢ Develop and maintain scripts using PowerShell, CMD and BAT for automation. "¢ Solid understanding and practical experience in version control(Git, Perforce). "¢ Embedded Windows software and good programming skills. "¢ Solid understanding of Operating System concepts. "¢ Windows and/or Linux kernel and development experience. "¢ Solid understanding of Python, C/C++/C#, SQL, Shell Scripting. "¢ Strong communication and interpersonal skills. "¢ Good problem solving and debugging skills. "¢ 2-5 years of Software Engineering or related work experience. "¢ C# and Python programming experience. "¢ Some experience with MS SQL Database development. "¢ Windows OS internals knowledge and experience "¢ Device driver debugging with WinDbg, JTAG/other tools. "¢ Basic knowledge of Processor architecture and cache subsystem. "¢ Experience with PC software - System BIOS, UEFI, ACPI, Drivers, Applications "¢ Basic knowledge of Jenkins and Artifactory. "¢ Experience with Windows program/driver development. "¢ Proficiency in using Visual Studio as an integrated development environment. "¢ ARM assembly "¢ Basic knowledge of Embedded OS (Kernel architecture, OS services heap, memory, multi-core, multi-threading, and crash debugging). Communication, written & interpersonal skills, motivation, the ability to learn quickly

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Looking for experienced embedded SW engineers interested in developing software for mobile/Auto/XR devices. Specifically, the position involves developing embedded software supporting Camera functions of Auto Mobile and XR Devices * Camera driver development. * Strong knowledge in LA,LE and Yocto build Infrastructure * Camera end-to-end use case design and feature implementation * Strong knowledge on Image processing. * Debugging and resolution with existing code base * Partnering with global development teams and with external customers * Some Onsite customers support * Power and performance optimization * Design and Implement component unit test for developer validation, test cases, test scenarios, scripts, or procedures with the target to ensure the best coverage of the requirements for each component. * Develops testing programs that assess effectiveness of a component or modification of an existing component. Ensure that Backward compatibility is maintained for each component. Candidate MUST have: Strong knowledge and experience in Camera Sensor, overview of image processing algorithm and V4L2 drivers. Strong C & C++ programming and debugging skills required. Strong knowledge in operating system fundamentals like virtual memory, CPU scheduling, process states, synchronization, etc. Strong knowledge in concepts like RTOS, RAM/Cache, Interrupt handling, etc applied to embedded systems. Hands on experience in Realtime issues like memory/stack corruption, ANR, deadlocks, race conditions, etc. Strong communication skills - able to understand and explain highly technical information in a clear and concise manner. Willing travel to customer sites and other Qualcomm office locations to co-develop next generation smartphones. Working Experience in any Multimedia technologies like camera/video framework is MUST. Good to have: Hands on experience in Camera driver development. Knowledge of camera sensor bring up, 3A algorithms, tuning experience. Familiar with Image quality Unit Test framework experience like CPPTest, GoogleTest. Minimum Qualifications: "¢ Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. "¢ 2+ years of work experience with Programming Language such as C, C++, Java, Python, etc. Qualifications: Bachelor"™s (BE/BTech) or Master"™s (MS/MTech) degree in camera/video framework with 9+ years of experience. Knowledge of Android Camera & Image processing. Profound understanding of System-on-Chip (SoC) architecture, Camera pipeline, memory subsystem architecture. Expertise in programming languages (C/C++) Strong debugging and analysis skills, including data and statistical analysis, and proficiency in performance & Power.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Good knowledge of C programming, Data Structures Exposure to embedded software and/or driver development Basic understanding of system level concepts such as Caches/DMA/IRQ handling is desired Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. Knowledge of basic network protocols (TCP/UDP/ARP) OR understanding of 802.11 specification is desired Exposure to Linux Kernel internals and experience with low level kernel programming such as writing/modifying networking/wireless LAN device drivers or Protocol handlers is a plus

Responsibilities Candidate should have experience in software development role, tools development, firmware development or validation tools development. Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He will be the key interface on processor Bringup Activities and own key debugs of architecture and micro-architecture issues during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must drive coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Technical Expertise:Very proficient in C programming, Strong Scripting skills. Over 10 years experience in hands on Software development using C, C++. Computer Architecture Knowledge:In-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. Multi-Processor Cache Coherency:Experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Operating Systems and Concepts:Atleast 5 years experience with Multithreading, context switching, memory management related development Preferred technical and professional experience IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience) ARM architecture RISC V architecture Spike simulator experience, QEMU simulator

Responsibilities As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 5+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Responsibilities -Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Responsibilities As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 5+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Responsibilities As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 3+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Responsibilities Candidate should have experience in Software development, tools development role, firmware development role or validation tools development. Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He will be working on processor Bringup Activities and own key debugs during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must work on coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Technical Expertise:Very proficient in C programming, Strong Scripting skills. Over 10 years experience in hands on Software development using C, C++. Computer Architecture Knowledge:In-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. Multi-Processor Cache Coherency:Experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Operating Systems and Concepts:Atleast 2 years experience with Multithreading, context switching, memory management related development Preferred technical and professional experience IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience) ARM architecture RISC V architecture Spike simulator experience, QEMU simulator

Responsibilities As a Logic design engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Good understanding of HW / SW co design / accelerators to enhance system level performance. Collaborate with the Chip development, Unit Verification, Physical design, testgen, millcode teams to develop the feature. Pre-Silicon:Signoff the Design that meets all the functional, area and timing goals. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise Experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core. Experience with VLSI Design in VHDL / Verilog logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution.

Mumps Intersystem Cache Developer Work Location: Chennai / Bangalore Work Type: Hybrid (2 to 3 days work from office per week) What you bring: Must have 4 -10 Years of experience in Mumps, GT.M/Cache, Linux and PL/SQL . Build tool:- SVN, Jira and Bit Bucket Administration :- GT.M installation and maintenance Linux Shell Scripting will be an additional advantage. It would be great to have knowledge on Banking Domain knowledge. What you will be doing: Design, code, test, implement, maintain and support applications software that is delivered on time and within budget. Work closely with customers, business analysts and team members to understand business requirements that drive analysis and design of quality technical solutions ensuring alignment with business and IT strategies and complying with FIS architectural standards. Provides application software development services or technical support typically in a defined project. Develops program logic for new applications or analyzes and modifies logic in existing applications. Codes, tests, debugs, documents, implements and maintains software applications. Maintains, tests and integrates application components. Makes recommendations towards the development of new code or reuse of existing code Ensures system improvements are successfully implemented. Demonstrates an understanding of FIS systems and the financial services industry. Career portal link to apply: https://careers.fisglobal.com/us/en/job/JR0293143/Mumps-Intersystem-Cache-Developer

Mumps Intersystem Cache Developer Work Location: Chennai / Bangalore Work Type: Hybrid (2 to 3 days work from office per week) What you bring: Must have 4 -10 Years of experience in Mumps, GT.M/Cache, Linux and PL/SQL . Build tool:- SVN, Jira and Bit Bucket Administration :- GT.M installation and maintenance Linux Shell Scripting will be an additional advantage. It would be great to have knowledge on Banking Domain knowledge. What you will be doing: Design, code, test, implement, maintain and support applications software that is delivered on time and within budget. Work closely with customers, business analysts and team members to understand business requirements that drive analysis and design of quality technical solutions ensuring alignment with business and IT strategies and complying with FIS architectural standards. Provides application software development services or technical support typically in a defined project. Develops program logic for new applications or analyzes and modifies logic in existing applications. Codes, tests, debugs, documents, implements and maintains software applications. Maintains, tests and integrates application components. Makes recommendations towards the development of new code or reuse of existing code Ensures system improvements are successfully implemented. Demonstrates an understanding of FIS systems and the financial services industry. Career portal link to apply: https://careers.fisglobal.com/us/en/job/JR0293143/Mumps-Intersystem-Cache-Developer