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Sequentia Technologies
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Backend VLSI Engineers (EMIR | Synthesis | Physical Design)

Backend VLSI Engineers (EMIR | Synthesis | Physical Design)

Sequentia Technologies

3 - 8 years

20 - 35 Lacs

hyderabad bengaluru

Posted:Just now| Platform:

Apply

Skills Required

physical design european market infrastructure regulation sta synthesis floor planning clp upf lec

Work Mode

Hybrid

Job Type

Full Time

Job Description

Location:

Experience:

Education:

Industry:

Open Positions

1. EMIR Engineer (510 Years)

Role & Responsibilities:

Block and sub-system level
EMIR sign-off
Run
BQM
for early power grid checks
Execute
static, dynamic and EM flows
Provide feedback to
PnR engineers
for closure
Develop
custom debug scripts
using Python / Perl

Skill Requirements:

Strong experience with
RHSC
(view creation commands)
Debug APIs knowledge (minimum 5 per view)
Basic understanding of
Voltus flows
Cross-domain knowledge:
PNR & STA basics
Python / Perl scripting

Good to Have:

In-depth
RHSC
and basic
Voltus
experience

2. Synthesis + LEC / CLP Engineer (Immediate | 3+ Years)

Role & Responsibilities:

Physical synthesis using
Fusion Compiler / Genus
Multi-corner, multi-mode optimization for
power, performance & area
Pre-STA analysis using
PrimeTime / Tempus
Low-power verification using
Conformal LP / VCLP
Verify constraint quality and completeness
Handle
functional ECO
and implementation support
Work closely with
RTL, DFT and PD teams

Skill Requirements:

Experience on
7nm / 5nm / advanced nodes
Strong understanding of
UPF and low-power concepts
Hands-on experience with
LEC / CLP flows
Proficient in
TCL / Perl / Shell scripting
Strong debugging and analytical skills

3. Physical Design Engineer (6–10 Years | 2 Positions)

Role & Responsibilities:

Independently handle
block/top-level physical design
PnR using
Fusion Compiler
Perform
CTS and timing closure
Physical verification using
Calibre
Ensure quality delivery and sign-off

Skill Requirements:

Strong experience in
Physical Design (PNR, PV)
Expertise in
CTS and timing closure

Good to Have:

EMIR analysis using
RedHawk / Voltus

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Backend VLSI Engineers (EMIR | Synthesis | Physical Design)

hyderabad, bengaluru

3.0 - 8.0 yrs

INR 20 - 35 Lacs

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Backend VLSI Engineers (EMIR | Synthesis | Physical Design)

Experience & Salary

Skills Required

Work Mode

Job Type

Job Description

Location:

Experience:

Education:

Industry:

Open Positions

1. EMIR Engineer (510 Years)

Role & Responsibilities:

EMIR sign-off

BQM

static, dynamic and EM flows

PnR engineers

custom debug scripts

Skill Requirements:

RHSC

Voltus flows

PNR & STA basics

Good to Have:

RHSC

Voltus

2. Synthesis + LEC / CLP Engineer (Immediate | 3+ Years)

Role & Responsibilities:

Fusion Compiler / Genus

power, performance & area

PrimeTime / Tempus

Conformal LP / VCLP

functional ECO

RTL, DFT and PD teams

Skill Requirements:

7nm / 5nm / advanced nodes

UPF and low-power concepts

LEC / CLP flows

TCL / Perl / Shell scripting

3. Physical Design Engineer (6–10 Years | 2 Positions)

Role & Responsibilities:

block/top-level physical design

Fusion Compiler

CTS and timing closure

Calibre

Skill Requirements:

Physical Design (PNR, PV)

CTS and timing closure

Good to Have:

RedHawk / Voltus

More Jobs at Sequentia Technologies