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Associate II - VLSI-Memory Layout-SV

Associate II - VLSI-Memory Layout-SV

0 years

|

0 Lacs

Bengaluru Karnataka India

Posted:2 weeks ago| Platform:

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Skills Required

layout compiler integration drc lvs verification cadence design synopsys checks dfm

Work Mode

On-site

Job Type

Full Time

Job Description

Role Description Memory Layout Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in memory layouts . Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines. Experience & or strong interest in memory compilers developed. Excellent and demonstrated team player with ability to work with external customers and in cross functional teams Skills Memory Layout,Finfet,Cadence,Layout Design Show more Show less

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Associate II - VLSI-Memory Layout-SV

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Bengaluru, Karnataka, India