Associate II - VLSI-Memory Layout-SV

You will be responsible for memory layout design, including important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. Your hands-on experience should include working with 16nm/14nm/10nm/7nm/Finfet process technologies. You will be expected to have expertise in top-level memory integration, DRC, LVS, density verification, and cleaning physicals across the compiler space. It is essential to have a good understanding of IR/EM related issues in memory layouts and experience with Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A strong knowledge of ultra-deep sub-micron layout design challenges and DFM guidelines is required. Experience or a strong interest in memory compilers is a plus. As a team player, you should be capable of working effectively with external customers and in cross-functional teams. Key Skills: Memory Layout, Finfet, Cadence, Layout Design About UST: UST is a global digital transformation solutions provider with a track record of partnering with leading companies for over 20 years. UST's approach is powered by technology, inspired by people, and led by purpose, supporting clients from design to operation. With a workforce of over 30,000 employees in 30 countries, UST aims to embed innovation and agility into its clients" organizations, making a boundless impact and touching billions of lives in the process.,