ASIC Physical Design Engineer

As an ASIC Physical Design Engineer, your primary role will be to oversee the physical implementation of ASIC designs while working closely with design and verification teams to ensure optimal performance. Your daily tasks will involve logic synthesis, floor planning, clock tree synthesis, physical verification, and timing closure. Additionally, you will be responsible for supporting RTL-to-GDSII flow development and optimization to meet PPA (Performance, Power, Area) goals. Key Responsibilities: - Execute the complete Physical Design Flow (RTL to GDSII) for high-speed, complex digital blocks or full-chip integration. - Perform Floorplanning and Power Grid (PDN) Synthesis to optimize for power delivery, area, and routing congestion. - Implement and optimize Placement and Clock Tree Synthesis (CTS) to achieve timing convergence and minimize clock skew and latency. - Drive Static Timing Analysis (STA) and timing closure across multiple corners and modes (setup and hold). - Perform Routing and post-route optimization for metal interconnects. - Ensure physical sign-off readiness by performing and resolving issues from Physical Verification checks, including Design Rule Check (DRC), Layout Versus Schematic (LVS), Antenna, and Electrical Rule Check (ERC). - Analyze and optimize designs for Power Integrity (IR-Drop and Electro-Migration) and Signal Integrity (Crosstalk) using industry-standard tools. - Develop and maintain design flow automation scripts (e.g., in Tcl, Python, Perl) to enhance efficiency and productivity. - Collaborate with front-end design, DFT, and architecture teams to define physical constraints and resolve design implementation issues. Qualifications Required: - Location: Ahmedabad, Bangalore - Job Type: Full-time - Experience Level: Any As an ASIC Physical Design Engineer, your primary role will be to oversee the physical implementation of ASIC designs while working closely with design and verification teams to ensure optimal performance. Your daily tasks will involve logic synthesis, floor planning, clock tree synthesis, physical verification, and timing closure. Additionally, you will be responsible for supporting RTL-to-GDSII flow development and optimization to meet PPA (Performance, Power, Area) goals. Key Responsibilities: - Execute the complete Physical Design Flow (RTL to GDSII) for high-speed, complex digital blocks or full-chip integration. - Perform Floorplanning and Power Grid (PDN) Synthesis to optimize for power delivery, area, and routing congestion. - Implement and optimize Placement and Clock Tree Synthesis (CTS) to achieve timing convergence and minimize clock skew and latency. - Drive Static Timing Analysis (STA) and timing closure across multiple corners and modes (setup and hold). - Perform Routing and post-route optimization for metal interconnects. - Ensure physical sign-off readiness by performing and resolving issues from Physical Verification checks, including Design Rule Check (DRC), Layout Versus Schematic (LVS), Antenna, and Electrical Rule Check (ERC). - Analyze and optimize designs for Power Integrity (IR-Drop and Electro-Migration) and Signal Integrity (Crosstalk) using industry-standard tools. - Develop and maintain design flow automation scripts (e.g., in Tcl, Python, Perl) to enhance efficiency and productivity. - Collaborate with front-end design, DFT, and architecture teams to define physical constraints and resolve design implementation issues. Qualifications Required: - Location: Ahmedabad, Bangalore - Job Type: Full-time - Experience Level: Any