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ASIC Engineer, RTL Integration

3 years

0 Lacs

bengaluru karnataka india

Posted:3 days ago| Platform: Linkedin logo

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Skills Required

integration electrical engineering design verilog checks ip power estimation timing security efficiency ai software research macro development systemverilog synthesis

Work Mode

On-site

Job Type

Full Time

Job Description

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation.
  • 3 years of experience with the Register-Transfer Level quality check tool flows (e.g., Lint, Clock Domain Crossing, Reset Domain Crossing, Synthesis).

Preferred qualifications:

  • Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC).
  • Experience with IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols and ASIC methodology.
  • Experience with methodologies for low power estimation, timing closure, synthesis.
  • Knowledge in one or more of these areas: Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin Multiplexing.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Define microarchitecture details for integration of Intellectual Property's(IPs) at macro/Sub-System Workload Requirements Plan (SSWRP) level.
  • Perform RTL development (SystemVerilog), debug functional/performance simulations.
  • Perform RTL quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, Unified Power Format (UPF) checks.
  • Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

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