ASIC Design Verification (DV) Lead

10 - 20 years

60 - 90 Lacs

Posted:16 hours ago| Platform: Naukri logo

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Hybrid

Job Type

Full Time

Job Description

Job Title:

Company:

About Cyient Semiconductor:

Cyient Semiconductor, a part of Cyient Ltd., is driving innovation across cutting-edge SoC, ASIC, and Mixed-Signal design programs for global customers. Our team combines deep domain expertise with world-class design and verification capabilities to deliver high-performance silicon solutions. Join us to be part of a dynamic organization shaping the next generation of semiconductor technologies.

Role Overview:

ASIC Design Verification Lead

DV Lead

Key Responsibilities:

  • Lead end-to-end

    ASIC/SoC Verification

    activities for block-level and full-chip environments.
  • Architect and develop

    UVM-based testbenches

    and reusable verification components.
  • Define

    verification strategy

    , test plans, and coverage goals to ensure design quality.
  • Drive

    functional, gate-level, and low-power (UPF)

    verification closure.
  • Collaborate with

    design, synthesis, DFT, and validation

    teams to ensure smooth handoff and debug cycles.
  • Manage verification deliverables, schedules, and task allocation for the team.
  • Mentor junior engineers and provide technical leadership across verification domains.
  • Support

    regression setup

    ,

    debug of complex simulation issues

    , and

    coverage analysis

    .

Required Skills and Experience:

  • 10-20 years

    of strong hands-on experience in

    ASIC/SoC Design Verification

    .
  • Excellent knowledge of

    Verilog

    ,

    System Verilog

    , and

    UVM methodology

    .
  • Proven experience in

    Testbench Architecture, Environment Development

    , and

    Functional Coverage

    .
  • Exposure to

    Gate-Level Simulations (GLS)

    ,

    Low-Power Verification (UPF/CPF)

    , and

    Power-Aware Simulations

    .
  • Familiarity with

    simulation and debugging tools

    (VCS, Incisive, Questa, Verdi, DVE, etc.).
  • Good understanding of ASIC design flow, synthesis, and timing concepts.
  • Strong analytical and problem-solving skills with an eye for detail.
  • Excellent communication and leadership abilities.

Good to Have:

  • Experience in

    SoC-level verification

    or

    subsystem integration

    .
  • Exposure to

    Assertion-Based Verification (ABV)

    and

    Formal Verification

    .
  • Working knowledge of

    Python/Perl/TCL scripting

    for automation.

Education:

  • B.E./B.Tech/M.E./M.Tech

    in Electronics, Electrical, or related field.

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