ASIC Design For Testability Engineer

Role Overview: The ideal candidate for this role should possess a Bachelor's or Master's degree or equivalent practical experience along with a minimum of 5 years of experience in Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies. You should have a proven track record in developing DFT specifications and DFT architecture, fault modeling, test standards, and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation, and verification flow. Key Responsibilities: - Experience with DFT for a subsystem with multiple physical partitions - Familiarity with Internal JTAG (IJTAG) ICL, Procedural Description Language (PDL) terminology, ICL extraction, Instrument Connectivity Language (ICL) modeling with Siemens Tessent Tool, Spyglass-DFT, DFT Scan constraints, and evaluating DFT Static Timing Analysis (STA) paths - Knowledge of coding languages like Perl or Python - Understanding of DFT techniques like SSN and HighBandwidth IJTAG Qualifications Required: - Bachelor's or Master's degree in a relevant field - Minimum of 5 years of experience in DFT/DFD flows and methodologies - Proficiency in developing DFT specifications and architecture - Strong knowledge of fault modeling, test standards, and industry tools - Experience with ASIC DFT, synthesis, simulation, and verification flow Additional Details: As a part of the team responsible for developing custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation in products that are loved by millions worldwide, delivering unparalleled performance, efficiency, and integration. Google's mission to organize the world's information and make it universally accessible and useful guides our work, combining the best of Google AI, Software, and Hardware to create radically helpful experiences. You will collaborate with Design for testing (DFT) engineers, Register-Transfer Level (RTL), Physical Designer Engineers, System on a chip (SoC) DFT, and Product Engineering team. Your responsibilities will include working on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains, writing scripts to automate the DFT flow, developing tests for Production in the Automatic Test Equipment (ATE) flow, and collaborating with the DFT team to deliver two or more Subsystems in a SoC.,