ASIC Design For Testability Engineer Google

5.0 - 9.0 years

0 Lacs

karnataka

On-site

Role Overview: The ideal candidate for this role should possess a Bachelor's or Master's degree or equivalent practical experience along with a minimum of 5 years of experience in Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies. You should have a proven track record in developing DFT specifications and DFT architecture, fault modeling, test standards, and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation, and verification flow. Key Responsibilities: - Experience with DFT for a subsystem with multiple physical partitions - Familiarity with Internal JTAG (IJTAG) ICL, Proce...

Posted 4 days ago

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