Verification Engineer

You should have 7 to 10 years of experience in module level and full chip functional verification. Your responsibilities will include creating test plans, developing test bench, coverage, and GLS. You must possess a minimum of 3 years of experience in System Verilog HVL and a minimum of 3 years of experience in OVM/UVM/VMM/Test Harness. Hands-on experience in developing assertion, checkers, coverage, and scenario creation is essential. It is required that you have executed at least 2 SoC Verification projects and have experience in developing test and coverage plans, Verification environment, and validation plans. Hands-on experience with one industry-standard protocol like Ethernet, PCIe, MIPI, USB, or similar is also necessary. Participation in reviews and audits is expected. Additionally, you should have at least 2 years of experience in handling a team of 5 to 10 engineers. Educational Qualifications: B.E., B.TECH, M.E., M.TECH.,