131 Upf Jobs - Page 6

You are best equipped for this task if you have: Should have experience of 5 years Strong Low Power Concepts including UPF IEEE format and constructs. Debug skills required on Synthesis run issues like : RTL not synthesizable, UPF, constraints related impact on Synthesis, Logical Equivalence Checking , Abort resolutions and Non Equivalence Debugging skills. Good to have Physical aware synthesis knowledge , LEF/DEF formats, basics of synthesis should be strong.

y Low Power UPF Front-End Design Engineer :- Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Low Power UPF Front-End Design Engineer :- Job Description: Deep expertise in low-power architecture, UPF-based power intent implementation, and front-end RTL methodologies. This role requires close collaboration with system architects, RTL design engineers, and back-end teams. Technical Requirement: Define and develop low-power architecture and strategies using Unified Power Format (UPF) Drive power intent specification, verification, and validation through all phases of the design lifecycle Collaborate with front-end design teams to ensure power-efficient RTL design, clock gating, power gating, voltage scaling, and retention strategies. Work closely with verification teams to develop power-aware simulation methodologies and tools. Perform power analysis, modeling, and trade-offs at the architectural and RTL level. Guide the synthesis and timing closure process with power intent considerations. Define and drive industry best practices in low-power methodologies, tools, and flows Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Drive and lead execution with SOC teams for Design. Drive efficiency on execution of SOC for integration as well as various quality checks like lint, CDC, RDC, Synthesis, CLP, LEC, constraints quality checks. Drive quality and timely delivery to various teams like DV, DFT, Emulation & PD. Work with architecture team on high level arch and uArch definition. Work with IP team for IP requirement, deliverables and negotiations. Drive SOC from concept to productization. Work with customer requirements on product definition, feature, bounding box analysis and drive optimal solution. Work with business and design team on optimal development cost solution considering in die size, power, performance optimization. Work with program management team for SOC planning, schedule, resource demand/supply, critical path analysis, dev cost and execution. Work with SOC (Design, DFT, DV, PD), System and SW team to deliver next generation high performance SOC designs. Work with post-Si team to drive Si bring up and ramp to productization. Drive improvisation on methodologies in SOC design. Get technical alignment with experts across geographies. Develop plans and track progress to maintain aggressive development timelines. Has understanding on SOC and IP development milestones and drive execution to meet them. THE PERSON: Strong understanding of SOC design methodology & related flows. (Design integration including UPF, Lint, CDC, RDC, CLP, LEC). Also on various handoffs (DV, PD, DFT & Emulation) Leader with strong self-driving ability and winning attitude. Be able to drive technical alignment with experts across geographies to improve design methodologies. Strong interpersonal and stakeholders management skills. Strong problem-solving skills. Strong commitment to own/drive SOC development using well-defined metrics. Work with PM team on execution planning, to track quality metrics, milestone convergence, to assess risk, and ensure plan is on track. Detail-oriented candidate who can work seamlessly with larger SOC design team across geographies on driving the solutions. Technical Leader with strong self-driving ability and winning attitude. Should have excellent communication written, oral and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. KEY RESPONSIBILITIES: Driving SOC design execution across from concept to tape-out and productization. Contribute to Bounding box analysis, Design, DFT, Verification, Test-plan, Power Reduction, Timing Convergence & Floorplan, Tape-outs, System engineering and SW deliverables. Running regular execution meetings, scrums, standing meetings and resolving bottlenecks. Project planning, schedule, deliverables, risk/ mitigations. Presenting status update to senior executives. Good understanding of sign-off flows like Lint, CDC, RDC, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows. Drive and improvise various design hand-offs to DV, DFT, PD and Emulation teams. Understanding design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle. Drive methodology development ideas/forums. Collaborate with CAD and EDA vendors to further strengthen AMD and S3 design methodology. Strong interpersonal skills to work across teams in different geographies. Provide technical direction, guidance, and Support to the engineering team. PREFERRED EXPERIENCE: Experience of successfully leading multiple SOC execution from spec to tape-out and productization. Expertise in SOC integration and implementation - IP Integration, SOC fabrics, Voltage / Clock domain crossings, DFT, Power intent design, RTL Quality checks, Clock, Reset, Fuses, Synthesis, Timing Analysis, Design Partitioning, PPA optimization, PnR, Timing analysis, Floorplan convergence, Physical design implementation and signoff. Experience in ASIC execution, customer engagement, deliverables and execution flow. Work with a team of Architects, Hardware and Software engineers to define the High-Level Architecture. Strong hands-on experience in different SOC design activities, Verification aspects, Test plan review, Debug/triage, bottleneck resolution etc. Strong Problem Solving and Debugging Skills Comfortable with design/implementation tools and flows like VCS, SOC Connectivity, Spyglass Lint/CDC/RDC, VCLP, Synthesis DC/FC, ICC, and Physical design implementation/signoff tools, STA and constraints analysis tools. Expertise in SOC architecture, System bus and IO protocol understanding (e.g. AXI, PCIe, Memory, uProcessor, etc.) Good understanding of System integration, multi-die methodology, packaging, yield, and system solution. Experience in working with SW team for BIOS, FW, Driver, SW stack, QA and SW release is a plus. Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks, and mitigation plan. Good understanding of Power, Performance and Area (PPA) optimization techniques. Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design. Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: ~5+ years of strong experience in leading end to end SOC design and ASIC execution. BE/B.Tech/ME/MTECH/MS or equivalent ECE/EEE with 12+ yrs. of experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas: Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.