Sr. Manager Silicon Design Engineering

We are looking for a Senior Manager Silicon Design Engineering to lead a team of talented engineers in developing NPU IP. This IP goes to several products including client and embedded products and serves as AI inference accelerator.

This role requires deep understanding of design implementation and flows, tools and methodologies.

THE PERSON

The ideal candidate should have demonstrated experience in leading front-end design and integration of sub-systems for complex SOCs.

The candidate must be able to communicate effectively and work optimally with different teams across AMD.The candidate must have excellent analytical and problem-solving skills.

KEY RESPONISIBILITES

• Manage design and front-end integration team for NPU.
• Drive the design execution using technical expertise, mentoring team of engineers & being responsible for overall execution Quality & schedule. Define and implement RTL design methodologies and best practices. Lead team, meet schedule commitments and provide strong support to various customers.
• Ensure Design meets performance, power and Area targets & verification coverage for successful silicon.
• Work with verification and physical design teams to achieve high quality design and successful tape out
• Collaborate with cross-functional team for successful and on-time delivery of NPU.

PREFERRED EXPERIENCES

• Strong design experience in ASIC designs, RTL design in Verilog/System Verilog, preferably in complex SOC like CPU/GPU.
• Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation
• Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power.
• Expertise in circuit timing/STA, and practical experience with Prime Time or equivalent tools
• Hands-on with TCL, Perl, Python scripting,
• Strong verbal and written communication skills