Sr. Manager Silicon Design Engineering

THE ROLE:

The ideal candidate will get to work on Verification of complex Analog Mixed Signal PHY IPs (with significant Digital and Analog content) that are delivered to various AMD SoCs.

KEY RESPONSIBILITIES:

• Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations.
• Create methodology-based (UVM) verification testbenches and components from scratch for various IP features.
• Quality deliverables through regressions
• Verification coverage:code-coverage, functional coverage, assertions, to achieve 100% verification completeness
• Reviews, and feedback to design/architecture teams.

PREFERRED EXPERIENCE:

• Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions
• Expertise in code and functional coverage,
• Excellent Problem solving and debugging skills.
• Excellent Communication skills
• Strong digital design knowledge, SoC design flow
• Knowledge on AMS designs (SERDES or Memory PHYs such as DDR, GDDR) and Mixed signal verification methodology is an added advantage.
• UPF based RTL low power verification
• Prior experience in working on IPs with mixed signal content will be helpful.
• Prior experience of technical leadership will be an asset.

ACADEMIC CREDENTIALS:

• Bachelor or Masters degree in ECE/EEE desired