Sr. Manager Silicon Design Engineering

Role Overview: As a Senior Manager Silicon Design Engineer at AMD, you will be responsible for working on the verification of complex Analog Mixed Signal PHY IPs with significant Digital and Analog content integrated into various AMD SoCs. Your main focus will be on creating feature test plans, developing verification testbenches, ensuring quality deliverables through regressions, and providing feedback to design/architecture teams. Key Responsibilities: - Verification of IP features: Create feature test plans, conduct verification of the IP in RTL, Gatesim, and Analog Mixed Signal simulations. - Develop methodology-based (UVM) verification testbenches and components from scratch for various IP features. - Ensure quality deliverables through regressions and achieve verification completeness through code-coverage, functional coverage, and assertions. - Provide reviews and feedback to design/architecture teams. Qualifications Required: - Expertise in System Verilog, UVM testbench architectures, System Verilog assertions, code and functional coverage. - Strong problem-solving, debugging, and communication skills. - Knowledge in digital design, SoC design flow, AMS designs, mixed signal verification methodology. - Experience in UPF based RTL low power verification and technical leadership. Additional Details: This position requires a Bachelor or Masters degree in ECE/EEE and is based in Bangalore. As part of the package for this role, AMD benefits are offered to employees.,