8 Silicon Design Jobs

As a Silicon Design Engineer at AMD, you will collaborate with formal experts and designers to verify formal properties and ensure convergence in the projects you work on. Your role will involve driving formal verification for the block, writing formal properties and assertions to verify the design, coordinating with RTL engineers to implement logic design for improved clock gating, and verifying various aspects of the design. Additionally, you will be responsible for writing tests, sequences, and testbench components in SystemVerilog and UVM, along with formal methods, to achieve thorough verification of the design. You will also play a crucial role in monitoring verification quality metrics such as pass rates, code coverage, and functional coverage. The ideal candidate for this position is someone with a strong passion for modern, complex processor architecture, digital design, and verification. You should possess excellent communication skills, be a team player, and have a knack for analytical thinking and problem-solving. A willingness to learn and tackle challenges head-on is essential for success in this role. To excel in this role, you should have project-level experience with design concepts and RTL implementation, familiarity with formal tools and functional verification tools such as VCS, Cadence, and Mentor Graphics, and a solid understanding of computer organization and architecture. A Bachelor's or Master's degree in computer engineering or Electrical Engineering is required to be considered for this position. At AMD, we are committed to transforming lives with our cutting-edge technology and innovative products. Join us in our mission to build products that enhance next-generation computing experiences across various industries. If you are passionate about pushing the limits of innovation and solving complex challenges, while embodying our core values of directness, humility, collaboration, and inclusivity, we invite you to be a part of our team and together, we advance.,

Job Details Job Description: Altera is looking for a talented and driven Silicon Design Engineering Manager to lead and inspire a multidisciplinary silicon design team. In this critical role, you will manage design engineers across multiple functional domainsincluding logic design, verification, circuit design, and physical implementationfor cutting-edge IP, subsystems, SoCs, and discrete chips. Youll be at the forefront of Alteras product innovation, driving high-quality silicon solutions that meet power, performance, area, and cost objectives. Key Responsibilities Lead and manage a team of silicon design engineers across multiple disciplines and development phases. Drive end-to-end development of IP blocks, subsystems, and full-chip SoC designs, ensuring on-time delivery with high quality. Oversee design reviews, ensuring power, performance, area (PPA), and cost targets are met. Collaborate with architecture, IP, and SoC development teams to ensure cohesive design and execution. Monitor verification results, conduct design debug, analyze data, and drive resolution of design issues. Implement and maintain rigorous silicon quality and continuous improvement standards. Optimize and evolve silicon development methodologies, tools, and processes. Set clear team goals, manage priorities, provide coaching, and foster a culture of accountability and high performance. Role model Altera and Intel values while creating an inclusive, productive, and innovative work environment. Minimum Requirements Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in silicon design, including at least 3 years in a management or technical leadership role. Proven track record managing full lifecycle silicon design projects from architecture through tape-out. Strong technical background in logic design, verification, and physical design. Deep understanding of PPA trade-offs and experience driving metrics-based decision making. Experience working across functional teams and global development environments. Preferred Qualifications Experience in SoC or FPGA-based design projects. Familiarity with industry-standard EDA tools and design methodologies. Demonstrated leadership in team building, performance management, and talent development. Strong communication and organizational skills. Qualifications Job Type: Regular Shift Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations: Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Show more Show less

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.?? THE PERSON: ? You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: ? Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues? Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: ? Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools? Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++?? Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributedcomputeenvironment.?? Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts andSystemVeriloglanguage Good working knowledge ofSystemCand TLM with some related experience.?? Scripting language experience: Perl, Ruby,Makefile, shell preferred.?? Exposure to leadership or mentorship is an asset Desirableassetswith prior exposure to video codec system or other multimedia solutions.?? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering

Silicon Design Engineer (RTL Design and Development) Responsible for RTL design and development Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools Perl, Python or TCL Scripting Email id- ta6@nipppondata.com

We are seeking a skilled Back End Developer with a focus on NodeJS to join our dynamic team. As a Back End Developer, you will be responsible for developing server-side logic, database integration, and ensuring high performance and responsiveness to requests from the front-end. We Eximietas Design About Eximietas History Careers Job Openings Connect Contact Us Engineer Silicon Silicon Design MicroArchitecture and RTL design Design Verification Physical Implementation Analog/Mixed Signal DFT Verification & Validation Presilicon Validation Post Silicon Validation Devices Embedded Software Firmware BSP & Drivers Multimedia Connectivity Edge AI Hardware Design Services High Speed Digital Design Hardware & Board Design Services Cloud & Digital Infrastructure & DevOps Secure Foundation Infrastructure as Code CI/CD Monitoring & Observability Modernization & Migration Workload Migration Application Development API & Application Integration Application Migration Modernize Applications Database Modernization Enterprise Database Migration Cyber Security Security Strategy & Compliance Identity & Access Management Infrastructure & Application Security Data Security & Privacy Threat Intelligence AI & Data Analytics AI & Machine Learning MLOps Conversational AI Generative AI Data Analytics Data Warehouse & Lake Modernization Business Intelligence & Data Visualization Excellence Why Eximietas Case Studies Blogs The Think Tank News and Events Click We Eximietas Design About Eximietas History Careers Job Openings Connect Contact Us Engineer Silicon Silicon Design MicroArchitecture and RTL design Design Verification Physical Implementation Analog/Mixed Signal DFT Verification & Validation Presilicon Validation Post Silicon Validation Devices Embedded Software Firmware BSP & Drivers Multimedia Connectivity Edge AI Hardware Design Services High Speed Digital Design Hardware & Board Design Services Cloud & Digital Infrastructure & DevOps Secure Foundation Infrastructure as Code CI/CD Monitoring & Observability Modernization & Migration Workload Migration Application Development API & Application Integration Application Migration Modernize Applications Database Modernization Enterprise Database Migration Cyber Security Security Strategy & Compliance Identity & Access Management Infrastructure & Application Security Data Security & Privacy Threat Intelligence AI & Data Analytics AI & Machine Learning MLOps Conversational AI Generative AI Data Analytics Data Warehouse & Lake Modernization Business Intelligence & Data Visualization Excellence Why Eximietas Case Studies Blogs The Think Tank News and Events Click Cloud / 3+ Years Back End Developer Bengaluru/Bhubaneswar Job Description We are seeking a skilled Back End Developer with a focus on NodeJS to join ourdynamic team. As a Back End Developer, you will be responsible for developing server-side logic, database integration, and ensuring high performance and responsiveness to requests from the front-end. You will collaborate with cross-functional teams to define, design, and ship new features and enhancements to our existing applications. The ideal candidate will have a strong understanding of Backend technologies, excellent problem-solving skills, and a passion for creating scalable and efficient systems. Responsibilities Design, develop, and maintain scalable, high-availability backend services using js. Develop RESTful APIs using js and Express to ensure seamless communication between the frontend and backend components. Integrate and manage databases, both relational (e.g., PostgreSQL) and/or NoSQL (e.g., MongoDB), to store, retrieve, and manipulate data Write clean, maintainable, and efficient code; perform code reviews to ensure code Implement thorough testing practices, including unit and integration testing, to maintain code quality and Requirements Bachelor s degree in computer science, Software Engineering, or a related 3+ years of professional experience as a Backend Developer, specializing in Strong command over js and Express for backend development. Solid experience with both SQL (e.g., PostgreSQL) and/or NoSQL (e.g., MongoDB) Familiarity with version control systems (e.g., Git) and agile development Excellent problem-solving skills and the ability to debug and troubleshoot complex technical Strong communication skills, both written and verbal, to collaborate effectively with technical and non-technical Strong experience with microservices architecture and system design. Preferred Qualifications Experience with cloud platforms such as AWS, Azure, or Google Cloud Knowledge of containerization technologies like Docker and orchestration tools such as Familiarity with continuous integration and continuous deployment (CI/CD) Understanding of Agile methodologies and DevOps