22 Silicon Design Jobs

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 4+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 4+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 12+years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

Implementation and verification of DFT architecture and features. Scan insertion and ATPG pattern generation. ATPG patterns verification with gate-level simulation. Test coverage and test cost reduction analysis. Post silicon support to ensure successful bring up and enhance yield learning. PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (e.g., IEEE1500, JTAG 1149.x, Scan, memory BIST etc.). Experience with Mentor TestKompress and/or Synopsys Tetramax/DFTMAX. Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: Strong knowledge in IP/SOC design methodologies. Power aware verification expertise using UPF (Unified Power Format) Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog Mentoring juniors and enhancing their skill set Must have strong knowledge of AMBA AHB/AXI protocol Working knowledge on code coverage, functional coverage, Lint, CDC etc IP development and coding using standard coding guide lines knowledge Excellent communication skills. Must be able to particpate lead in global meetings Soft skills to be able to work in a cross functional international team digital and software design engineers Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requireme PREFERRED EXPERIENCE: 6+ Years for experience Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Experience with power-aware verification methodologies and UPF Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.

You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models Work with the post-silicon team on debug support and to help root-cause any failures Be upto date with the industry trends and bring-in the latest to the AMD products Work with DFT Tool Vendors and drive improvements based on our requirements REQUIREMENTS: 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes. Good understanding and exposure to SoC design and architecture Very good understanding of verif and timing concepts having handled DFT timing closure Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc Comfortable with VCS/Verdi and Mentor TK. Logical in thinking and ability to gel we'll within a team Good stakeholder management Ability to quickly adapt to changes and handle pressure Good communication and leadership skills

Isolate generic system level failures into a more focused area of the platform or CPU Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Develop x86 content to exercise new features and reproduce complex bugs in silicon Devise validation strategy from pre-silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams Proactively participating in project planning, developing, and maintaining schedules, managing dependencies, and ensuring quality of deliverables at committed milestones. Generates/Maintains regular status representing the Server Validation team in program meetings providing status to program management PREFERRED EXPERIENCE: Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) x86 assembly programming Debug techniques and methodologies Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion

We are looking for a Senior Manager Silicon Design Engineering to lead a team of talented engineers in developing NPU IP. This IP goes to several products including client and embedded products and serves as AI inference accelerator. This role requires deep understanding of design implementation and flows, tools and methodologies. THE PERSON : The ideal candidate should have demonstrated experience in leading front-end design and integration of sub-systems for complex SOCs. The candidate must be able to communicate effectively and work optimally with different teams across AMD.The candidate must have excellent analytical and problem-solving skills. KEY RESPONISIBILITES : Manage design and front-end integration team for NPU. Drive the design execution using technical expertise, mentoring team of engineers & being responsible for overall execution Quality & schedule. Define and implement RTL design methodologies and best practices. Lead team, meet schedule commitments and provide strong support to various customers. Ensure Design meets performance, power and Area targets & verification coverage for successful silicon. Work with verification and physical design teams to achieve high quality design and successful tape out Collaborate with cross-functional team for successful and on-time delivery of NPU. PREFERRED EXPERIENCES : Strong design experience in ASIC designs, RTL design in Verilog/System Verilog, preferably in complex SOC like CPU/GPU. Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power. Expertise in circuit timing/STA, and practical experience with Prime Time or equivalent tools Hands-on with TCL, Perl, Python scripting, Strong verbal and written communication skills

As a Silicon Design Engineer at AMD, you will have the opportunity to work with formal experts and designers to verify formal properties and drive convergence. Your passion for modern, complex processor architecture, digital design, and verification will be put to good use in this role. You will be a key team player with excellent communication skills, strong analytical abilities, and problem-solving skills. Your willingness to learn and readiness to take on challenges will be crucial for success in this position. Your key responsibilities will include driving formal verification for the block, writing formal properties and assertions to verify the design, coordinating with RTL engineers to implement logic design for better clock gating, and verifying various aspects of the design. You will also be responsible for writing tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design. Additionally, you will be accountable for verification quality metrics such as pass rates, code coverage, and functional coverage. Preferred experience for this role includes project-level experience with design concepts and RTL implementation, familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics, and a good understanding of computer organization/architecture. To qualify for this position, you should hold a Bachelor's or Master's degree in computer engineering or Electrical Engineering. Join AMD to be part of a culture that pushes the limits of innovation to solve the world's most important challenges. Together, we advance the building blocks for next-generation computing experiences in the data center, artificial intelligence, PCs, gaming, and embedded systems. At AMD, we strive for execution excellence while embodying qualities of being direct, humble, collaborative, and inclusive of diverse perspectives.,

Leads and manages silicon design teams that span across more than one area of functional development including logic design, verification, circuit design, and/or physical design for an IP, sub-system, SoC, and/or discrete chip. Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards. Conducts design reviews to ensure key factors such as power, performance, area, and cost are meeting requirements. Works to continuously to improve silicon development processes and architecture definition across areas of silicon design. Oversees and reviews design verification test results, data analysis, issue tracking, root cause analysis, and drives corrective actions implementation for silicon design. Works closely across IP and SoC development teams to design complex projects, ensure quality, drive performance, and design implementation. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.,

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Additionally, you have 10 years of experience in ASIC hardware architecture and silicon design. Ideally, you also possess a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Your background includes experience with processor core architectures (such as ARM, x86, RISC-V, etc.) and IPs commonly used in SoC designs. Moreover, you have expertise in architecting and designing low power ASIC hardware IP for complex SoCs in various areas like camera ISP, video codecs, display, graphics, and machine learning networks. You have also worked with ambient or always-on vision hardware and workflows for ultra-low power SoC applications. As a member of our team, you will be involved in developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will play a vital role in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration for products that are beloved by millions globally. At Google, we are committed to organizing the world's information and making it universally accessible and useful. Our team leverages the synergy of Google AI, Software, and Hardware to create innovative and impactful experiences. We are constantly researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately aiming to improve people's lives through technology. Your responsibilities will include defining and delivering the hardware Multimedia/Graphics ASIC IP architecture to meet competitive power, performance, area, and image quality objectives. This role requires you to collaborate closely with Graphics, Camera, Video, Display, and ML software, system, and algorithm engineers to co-develop and specify competitive hardware IP architectures for integration into complex SoCs. You will work with GPU, TPU, camera ISP, video, and display hardware IP design teams across global sites to drive the hardware IP architecture specifications into design implementation for complex SoCs. In addition, you will collaborate with SoC and System/Experience architects to meet rigorous power, performance, and area requirements at the SoC level for multimedia use cases and experiences. Data analysis and tradeoff evaluations will also be part of your responsibilities to enhance multimedia architecture solutions.,

As a Silicon Design Engineer 2 at AMD, your role involves collaborating with formal experts and designers to verify formal properties and drive convergence. You will have the opportunity to work on modern, complex processor architecture, digital design, and verification in a team-oriented environment. Your strong analytical and problem-solving skills will be pivotal in understanding design specifications and creating scenarios to verify the design effectively. Communication skills are essential as you coordinate with RTL engineers to implement logic design for improved clock gating and verify different aspects of the design. Your responsibilities will include writing tests, sequences, and testbench components in SystemVerilog and UVM to achieve verification of the design. You will be accountable for verification quality metrics such as pass rates, code coverage, and functional coverage. Prior experience in design concepts and RTL implementation at the project level would be advantageous. Familiarity with formal tools and functional verification tools by VCS, Cadence, or Mentor Graphics is preferred. A solid understanding of computer organization and architecture is also important for this role. To excel in this position, you should possess a Bachelor's or Master's degree in computer engineering or Electrical Engineering. AMD offers a supportive work culture that values innovation, collaboration, and diversity. Join us in advancing next-generation computing experiences and being part of a team that pushes the boundaries of technology.,

As a Silicon Design Engineer at AMD, you will collaborate with formal experts and designers to verify formal properties and ensure convergence in the projects you work on. Your role will involve driving formal verification for the block, writing formal properties and assertions to verify the design, coordinating with RTL engineers to implement logic design for improved clock gating, and verifying various aspects of the design. Additionally, you will be responsible for writing tests, sequences, and testbench components in SystemVerilog and UVM, along with formal methods, to achieve thorough verification of the design. You will also play a crucial role in monitoring verification quality metrics such as pass rates, code coverage, and functional coverage. The ideal candidate for this position is someone with a strong passion for modern, complex processor architecture, digital design, and verification. You should possess excellent communication skills, be a team player, and have a knack for analytical thinking and problem-solving. A willingness to learn and tackle challenges head-on is essential for success in this role. To excel in this role, you should have project-level experience with design concepts and RTL implementation, familiarity with formal tools and functional verification tools such as VCS, Cadence, and Mentor Graphics, and a solid understanding of computer organization and architecture. A Bachelor's or Master's degree in computer engineering or Electrical Engineering is required to be considered for this position. At AMD, we are committed to transforming lives with our cutting-edge technology and innovative products. Join us in our mission to build products that enhance next-generation computing experiences across various industries. If you are passionate about pushing the limits of innovation and solving complex challenges, while embodying our core values of directness, humility, collaboration, and inclusivity, we invite you to be a part of our team and together, we advance.,

Job Details Job Description: Altera is looking for a talented and driven Silicon Design Engineering Manager to lead and inspire a multidisciplinary silicon design team. In this critical role, you will manage design engineers across multiple functional domainsincluding logic design, verification, circuit design, and physical implementationfor cutting-edge IP, subsystems, SoCs, and discrete chips. Youll be at the forefront of Alteras product innovation, driving high-quality silicon solutions that meet power, performance, area, and cost objectives. Key Responsibilities Lead and manage a team of silicon design engineers across multiple disciplines and development phases. Drive end-to-end development of IP blocks, subsystems, and full-chip SoC designs, ensuring on-time delivery with high quality. Oversee design reviews, ensuring power, performance, area (PPA), and cost targets are met. Collaborate with architecture, IP, and SoC development teams to ensure cohesive design and execution. Monitor verification results, conduct design debug, analyze data, and drive resolution of design issues. Implement and maintain rigorous silicon quality and continuous improvement standards. Optimize and evolve silicon development methodologies, tools, and processes. Set clear team goals, manage priorities, provide coaching, and foster a culture of accountability and high performance. Role model Altera and Intel values while creating an inclusive, productive, and innovative work environment. Minimum Requirements Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in silicon design, including at least 3 years in a management or technical leadership role. Proven track record managing full lifecycle silicon design projects from architecture through tape-out. Strong technical background in logic design, verification, and physical design. Deep understanding of PPA trade-offs and experience driving metrics-based decision making. Experience working across functional teams and global development environments. Preferred Qualifications Experience in SoC or FPGA-based design projects. Familiarity with industry-standard EDA tools and design methodologies. Demonstrated leadership in team building, performance management, and talent development. Strong communication and organizational skills. Qualifications Job Type: Regular Shift Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations: Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Show more Show less

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.?? THE PERSON: ? You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: ? Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues? Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: ? Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools? Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++?? Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributedcomputeenvironment.?? Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts andSystemVeriloglanguage Good working knowledge ofSystemCand TLM with some related experience.?? Scripting language experience: Perl, Ruby,Makefile, shell preferred.?? Exposure to leadership or mentorship is an asset Desirableassetswith prior exposure to video codec system or other multimedia solutions.?? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering

Silicon Design Engineer (RTL Design and Development) Responsible for RTL design and development Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools Perl, Python or TCL Scripting Email id- ta6@nipppondata.com

We are seeking a skilled Back End Developer with a focus on NodeJS to join our dynamic team. As a Back End Developer, you will be responsible for developing server-side logic, database integration, and ensuring high performance and responsiveness to requests from the front-end. We Eximietas Design About Eximietas History Careers Job Openings Connect Contact Us Engineer Silicon Silicon Design MicroArchitecture and RTL design Design Verification Physical Implementation Analog/Mixed Signal DFT Verification & Validation Presilicon Validation Post Silicon Validation Devices Embedded Software Firmware BSP & Drivers Multimedia Connectivity Edge AI Hardware Design Services High Speed Digital Design Hardware & Board Design Services Cloud & Digital Infrastructure & DevOps Secure Foundation Infrastructure as Code CI/CD Monitoring & Observability Modernization & Migration Workload Migration Application Development API & Application Integration Application Migration Modernize Applications Database Modernization Enterprise Database Migration Cyber Security Security Strategy & Compliance Identity & Access Management Infrastructure & Application Security Data Security & Privacy Threat Intelligence AI & Data Analytics AI & Machine Learning MLOps Conversational AI Generative AI Data Analytics Data Warehouse & Lake Modernization Business Intelligence & Data Visualization Excellence Why Eximietas Case Studies Blogs The Think Tank News and Events Click We Eximietas Design About Eximietas History Careers Job Openings Connect Contact Us Engineer Silicon Silicon Design MicroArchitecture and RTL design Design Verification Physical Implementation Analog/Mixed Signal DFT Verification & Validation Presilicon Validation Post Silicon Validation Devices Embedded Software Firmware BSP & Drivers Multimedia Connectivity Edge AI Hardware Design Services High Speed Digital Design Hardware & Board Design Services Cloud & Digital Infrastructure & DevOps Secure Foundation Infrastructure as Code CI/CD Monitoring & Observability Modernization & Migration Workload Migration Application Development API & Application Integration Application Migration Modernize Applications Database Modernization Enterprise Database Migration Cyber Security Security Strategy & Compliance Identity & Access Management Infrastructure & Application Security Data Security & Privacy Threat Intelligence AI & Data Analytics AI & Machine Learning MLOps Conversational AI Generative AI Data Analytics Data Warehouse & Lake Modernization Business Intelligence & Data Visualization Excellence Why Eximietas Case Studies Blogs The Think Tank News and Events Click Cloud / 3+ Years Back End Developer Bengaluru/Bhubaneswar Job Description We are seeking a skilled Back End Developer with a focus on NodeJS to join ourdynamic team. As a Back End Developer, you will be responsible for developing server-side logic, database integration, and ensuring high performance and responsiveness to requests from the front-end. You will collaborate with cross-functional teams to define, design, and ship new features and enhancements to our existing applications. The ideal candidate will have a strong understanding of Backend technologies, excellent problem-solving skills, and a passion for creating scalable and efficient systems. Responsibilities Design, develop, and maintain scalable, high-availability backend services using js. Develop RESTful APIs using js and Express to ensure seamless communication between the frontend and backend components. Integrate and manage databases, both relational (e.g., PostgreSQL) and/or NoSQL (e.g., MongoDB), to store, retrieve, and manipulate data Write clean, maintainable, and efficient code; perform code reviews to ensure code Implement thorough testing practices, including unit and integration testing, to maintain code quality and Requirements Bachelor s degree in computer science, Software Engineering, or a related 3+ years of professional experience as a Backend Developer, specializing in Strong command over js and Express for backend development. Solid experience with both SQL (e.g., PostgreSQL) and/or NoSQL (e.g., MongoDB) Familiarity with version control systems (e.g., Git) and agile development Excellent problem-solving skills and the ability to debug and troubleshoot complex technical Strong communication skills, both written and verbal, to collaborate effectively with technical and non-technical Strong experience with microservices architecture and system design. Preferred Qualifications Experience with cloud platforms such as AWS, Azure, or Google Cloud Knowledge of containerization technologies like Docker and orchestration tools such as Familiarity with continuous integration and continuous deployment (CI/CD) Understanding of Agile methodologies and DevOps