28 Silicon Design Jobs

Directs and manages a team of physical design engineers responsible for the physical design implementation of a chip design, subsystem, or block including clocking, timing, and integration. Provides guidance on physical design implementation and analyzes layout designs, power delivery, place, route, clock tree synthesis, and other aspects of physical design. Manages development of complex layout integrated circuit designs, simulation designs, RTL to GDS, logic synthesis, and oversees documentation for SoC development. Reviews circuit layouts architectures and prototypes, ensures issue resolution, and optimizes circuit output. Oversees physical design verification flow at block and chip level...

As an experienced professional in ASIC hardware architecture and silicon design, you will have the opportunity to be part of a team that is at the forefront of developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will play a key role in shaping the future of hardware experiences, focusing on delivering unparalleled performance, efficiency, and integration. **Key Responsibilities:** - Define and deliver the hardware Multimedia/Graphics ASIC IP architecture to meet power, performance, area, and image quality goals from inception to product launch. - Collaborate with Graphics, Camera, Video, Display, and ML software engineers to co-develop hardware IP...

Role Overview: You will lead and manage silicon design teams working on various areas of functional development such as logic design, verification, circuit design, and physical design for different types of chips like IP, sub-system, SoC, and discrete chip. Your role will involve managing team resources, functions, activities, responsibilities, and ensuring continuous improvement in silicon quality standards. You will conduct design reviews to guarantee that key factors like power, performance, area, and cost meet the requirements. Additionally, you will work on enhancing silicon development processes and architecture definition across different areas of silicon design. Collaboration with IP...

As an experienced ASIC hardware architect, you will play a vital role in developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will drive innovation in products that are loved by millions worldwide. You will have the opportunity to shape the next generation of hardware experiences, focusing on performance, efficiency, and integration. **Key Responsibilities:** - Define and deliver the hardware Multimedia/Graphics ASIC IP architecture to meet power, performance, area, and image quality goals from inception to product launch. - Collaborate with software, system, and algorithm engineers to co-develop and specify hardware IP architectures for integratio...

Job Details Job Description: Altera is looking for a talented and driven Silicon Design Engineering Manager to lead and inspire a multidisciplinary silicon design team. In this critical role, you will manage design engineers across multiple functional domainsincluding logic design, verification, circuit design, and physical implementationfor cutting-edge IP, subsystems, SoCs, and discrete chips. You'll be at the forefront of Altera's product innovation, driving high-quality silicon solutions that meet power, performance, area, and cost objectives. Key Responsibilities Lead and manage a team of silicon design engineers across multiple disciplines and development phases. Drive end-to-end devel...

In this role as a Silicon Design Engineer at AMD, you will have the opportunity to work alongside formal experts and designers to verify formal properties and drive convergence. Your passion for modern, complex processor architecture, digital design, and verification will be essential as you contribute to the success of the team. As a team player with excellent communication skills, strong analytical abilities, and a willingness to learn, you will play a key role in ensuring the quality and effectiveness of the design verification process. Key Responsibilities: - Drive formal verification for the block and develop formal properties and assertions for design verification - Collaborate with RT...

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PRE...

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PRE...

Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling differen...

AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Cro...

Implementation and verification of DFT architecture and features. Scan insertion and ATPG pattern generation. ATPG patterns verification with gate-level simulation. Test coverage and test cost reduction analysis. Post silicon support to ensure successful bring up and enhance yield learning. PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (e.g., IEEE1500, JTAG 1149.x, Scan, memory BIST etc.). Experience with Mentor TestKompress and/or Synopsys Tetramax/DFTMAX. Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Gr...

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: Strong knowledge in IP/SOC design methodologies. Power aware verification expertise using UPF (Unified Power Format) Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog Mentoring juniors and enhancing their skill set Must have strong knowledge of AMBA AHB/AXI protocol Working knowledge on ...

You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug...

Isolate generic system level failures into a more focused area of the platform or CPU Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Develop x86 content to exercise new features and reproduce complex bugs in silicon Devise validation strategy from pre-silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams Proactively participating in project planning, developing, and maintaining schedules, managing dependencies, and ensuring quality of deliverables at committed milestones. Generates/Maintains regular status representing the Server Validation te...

We are looking for a Senior Manager Silicon Design Engineering to lead a team of talented engineers in developing NPU IP. This IP goes to several products including client and embedded products and serves as AI inference accelerator. This role requires deep understanding of design implementation and flows, tools and methodologies. THE PERSON : The ideal candidate should have demonstrated experience in leading front-end design and integration of sub-systems for complex SOCs. The candidate must be able to communicate effectively and work optimally with different teams across AMD.The candidate must have excellent analytical and problem-solving skills. KEY RESPONISIBILITES : Manage design and fr...

As a Silicon Design Engineer at AMD, you will have the opportunity to work with formal experts and designers to verify formal properties and drive convergence. Your passion for modern, complex processor architecture, digital design, and verification will be put to good use in this role. You will be a key team player with excellent communication skills, strong analytical abilities, and problem-solving skills. Your willingness to learn and readiness to take on challenges will be crucial for success in this position. Your key responsibilities will include driving formal verification for the block, writing formal properties and assertions to verify the design, coordinating with RTL engineers to ...

Leads and manages silicon design teams that span across more than one area of functional development including logic design, verification, circuit design, and/or physical design for an IP, sub-system, SoC, and/or discrete chip. Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards. Conducts design reviews to ensure key factors such as power, performance, area, and cost are meeting requirements. Works to continuously to improve silicon development processes and architecture definition across areas of silicon design. Oversees and reviews design verification test results, data analysis, issue track...

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Additionally, you have 10 years of experience in ASIC hardware architecture and silicon design. Ideally, you also possess a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Your background includes experience with processor core architectures (such as ARM, x86, RISC-V, etc.) and IPs commonly used in SoC designs. Moreover, you have expertise in architecting and designing low power ASIC hardware IP for complex SoCs in various areas like camera ISP, video codecs, dis...

As a Silicon Design Engineer 2 at AMD, your role involves collaborating with formal experts and designers to verify formal properties and drive convergence. You will have the opportunity to work on modern, complex processor architecture, digital design, and verification in a team-oriented environment. Your strong analytical and problem-solving skills will be pivotal in understanding design specifications and creating scenarios to verify the design effectively. Communication skills are essential as you coordinate with RTL engineers to implement logic design for improved clock gating and verify different aspects of the design. Your responsibilities will include writing tests, sequences, and te...

As a Silicon Design Engineer at AMD, you will collaborate with formal experts and designers to verify formal properties and ensure convergence in the projects you work on. Your role will involve driving formal verification for the block, writing formal properties and assertions to verify the design, coordinating with RTL engineers to implement logic design for improved clock gating, and verifying various aspects of the design. Additionally, you will be responsible for writing tests, sequences, and testbench components in SystemVerilog and UVM, along with formal methods, to achieve thorough verification of the design. You will also play a crucial role in monitoring verification quality metric...

Job Details Job Description: Altera is looking for a talented and driven Silicon Design Engineering Manager to lead and inspire a multidisciplinary silicon design team. In this critical role, you will manage design engineers across multiple functional domainsincluding logic design, verification, circuit design, and physical implementationfor cutting-edge IP, subsystems, SoCs, and discrete chips. Youll be at the forefront of Alteras product innovation, driving high-quality silicon solutions that meet power, performance, area, and cost objectives. Key Responsibilities Lead and manage a team of silicon design engineers across multiple disciplines and development phases. Drive end-to-end develop...

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Expe...

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Expe...

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Expe...