Staff Engineer - RTL Design with SDC (Static Design Constraints)

As a Timing Expert at Alphawave Semi, you will play a crucial role in accelerating critical data communication essential for digital innovation. Your responsibilities will include: - Developing block and full-chip SDC methodology, creating clocking diagrams, and resolving timing issues to ensure design closure for performance, power, and area (PPA). - Collaborating with RTL and physical design teams to create and manage accurate constraints for successful timing closure. - Analyzing and debugging timing violations using industry-standard tools, optimizing design for PPA through timing analysis and constraint tuning. - Mentoring other designers on SDC development best practices and participating in design reviews to provide technical expertise on timing-related matters. Qualifications required for this role include: - Education: Bachelor's or Master's degree in Electronics Engineering or a related field. - Experience: 8+ years of experience with ASIC design flow, including RTL design and logic synthesis, with a crucial understanding of SDC. - Timing Expertise: Deep understanding of static timing analysis concepts, clocking, and timing exceptions. - Tools: Proficiency in industry-standard SDC and STA tools, along with strong scripting skills (e.g., Python, Perl) for automation. - Collaboration: Ability to work effectively with cross-functional teams and strong analytical skills for problem-solving complex timing issues. Additionally, Alphawave Semi offers a comprehensive benefits package, including competitive compensation, RSUs, a hybrid working model, provisions for advanced education, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snacks facility. At Alphawave Semi, we are committed to equality and diversity, providing accommodations during the recruitment process to ensure equal opportunities for all applicants.,