RTL ASIC Engineer (All Levels) Blueberry Semiconductors

1.0 - 15.0 years

0 Lacs

karnataka

On-site

You should be an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog. Your expertise should cover all aspects of the RTL design flow, including Specification/Microarchitecture definition, design and verification, Timing Analysis, DFT, and Implementation. You should also have experience in Integration, RTL signoff tools, UPF/Low power signoff, CDC/RDC, and Lint. Your domain knowledge should be strong in Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. As a highly motivated individual, you should be a self-starter with excellent interpersonal skills and the ability to work effectively in a team. Strong communication, critical thinking, and problem-solving skills are essential for this role. Preferred education for this position is any degree.,

Posted 1 week ago

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