8 Clocking Jobs

As an Analog Circuit Design professional at Cadence, you will play a critical role in shaping the world of technology. With 2+ to 8 years of experience, your expertise will be utilized in our Hyderabad office. Your educational background should include a BE/B Tech/ME/M Tech/MS degree, and a deep understanding of high-speed Serdes/Memory interface circuits such as I/Os, PLLs, Clocking, and Datapaths is essential. Your hands-on experience with PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits will be highly valued. Proficiency in Analog Design, I/O Design fundamentals, and knowledge of ESD/Reliability/SI/PI is crucial. You will be expected to lead complex IPs, manage cross-functional dependencies, and mentor junior engineers. Moreover, prior exposure to advanced technology nodes like 16nm/10nm/12nm/7nm will be considered a significant advantage. Excellent written and verbal communication skills, along with strong problem-solving abilities, are essential for this role. At Cadence, we are committed to making a meaningful impact through our work. Join us in solving challenges that others cannot.,

We are looking for a highly experienced Clocking/Constraints/STA Lead to join our Physical Design team. In this critical leadership role, you will not only be responsible for your own technical expertise but also for guiding and mentoring a team of engineers to achieve exceptional timing closure for our IC designs. Lead the development and implementation of comprehensive clocking strategies for high-performance ICs. Define and manage timing constraints throughout the design flow, ensuring accurate and consistent timing analysis. Perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks. Develop and maintain robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control. Drive the creation and execution of a comprehensive clock domain crossing (CDC) verification plan. Collaborate with design engineers, layout engineers, and other physical design teams to address timing closure challenges. Mentor and coach junior engineers, fostering their growth and expertise in clocking, constraints, and STA. Stay up-to-date with the latest advancements in clocking methodologies, timing analysis tools, and industry best practices. Lead the evaluation and implementation of new tools and methodologies for improved timing closure efficiency. Develop and maintain comprehensive documentation for clocking, constraints, and STA practices within the team. Qualifications: - Master's degree in Electrical Engineering, Computer Engineering, or a related field (preferred) or Bachelor's degree with extensive experience. - Minimum of 10+ years of experience in clocking, constraints, and STA for digital IC design. - Proven leadership experience in managing and motivating a team of engineers. - In-depth knowledge of digital design principles, timing analysis methodologies, and clock tree synthesis techniques. - Expert-level proficiency in industry-standard STA tools (e.g., Synopsys PrimeTime, Mentor Questa Timing Analyzer). - Strong understanding of clock domain crossing (CDC) verification concepts and methodologies. - Excellent communication, collaboration, and interpersonal skills. - Ability to think strategically, solve complex timing closure problems, and make sound technical decisions. - Proven ability to manage multiple projects and meet aggressive deadlines in a fast-paced environment.,

Qualcomm India Private Limited is a leading technology innovator that aims to create a smarter, connected future for all by pushing the boundaries of what's possible and driving digital transformation. As a Qualcomm Hardware Engineer within the Engineering Group, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3 years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience is also acceptable. A minimum of 4 to 6 years of work experience in ASIC RTL Design is required. Hands-on experience in Logic design/micro-architecture/RTL coding, as well as design and integration of complex multi clock domain blocks, is a must. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, APB are essential. Experience in Multi Clock designs, Asynchronous interface, and using tools in ASIC development like Lint, CDC, Design compiler, and Primetime is necessary. Understanding of Automotive System Designs, Functional Safety, Memory controller designs, and microprocessors is an added advantage. As a Qualcomm Hardware Engineer, you will work closely with Design verification and validation teams for pre/post Silicon debug. Hands-on experience in Low power design is preferable, and familiarity with Synthesis/Understanding of timing concepts for ASIC is a must. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. The company expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies are not authorized to use the site for submissions. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation teams for pre/post Silicon debug is expected, and hands-on experience in Low power design is preferable. Additionally, experience in Synthesis and understanding of timing concepts for ASIC is essential. The minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in the relevant fields with 2+ years of experience or a PhD with 1+ year of experience would also be considered. Qualcomm is an equal opportunity employer committed to providing accessibility to individuals with disabilities throughout the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Employees are expected to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not bear responsibility for any fees related to such submissions. For more information about this role, please contact Qualcomm Careers.,

The job involves designing and developing FPGA circuits and IPs, which includes core fabric logic, routing, clocking, memory blocks, and network on chip. You will be responsible for micro-architecting and performing circuit and logic design, schematic entry, simulation, reliability verification, and ensuring functionality optimization for power, performance, area, timing, and yield goals. Additionally, you will develop models and collaterals for FPGA circuits and IPs to integrate into hardware and software deliverables. Collaboration with teams in different time zones is essential to deliver high-quality products. To qualify for this role, you must have a Bachelor's degree in Electrical/Electronic Engineering or Computer Engineering. More than 5 years of experience in CMOS circuit design is preferred. You should be capable of reviewing designs within a team and have a good understanding of the physics behind the latest CMOS design processes, as well as layout-dependent impacts on performance, power, and area. This is a regular job with Shift 1 (India) as the primary location, with additional locations in Virtual - IND and Penang 16. Join us in this dynamic role where you will play a key part in designing cutting-edge FPGA circuits and IPs to deliver best-in-class products.,

Foundry Services (FS) is an independent foundry business established to meet customers" unique product needs. With the first Open System Foundry model globally, combined offerings include wafer fabrication, advanced process, packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities. This helps customers build innovative silicon designs and deliver customizable products from Intel's secure, resilient, and sustainable supply source. This job opportunity in FS will be part of the Customer Solutions Engineering (CSE) group, responsible for bringing the best of Intel technologies to FS customers, accelerating solutions from architecture to post-silicon validation. We are seeking an experienced Floorplan Engineer to focus on floor plan, die estimation, and power planning for high-performance designs. Responsibilities include establishing integration plans for die with optimization for package and board constraints, bump planning, die file generation, collaborating with architects for IP or SoC placement optimization, clocking and dataflow collaboration, deriving specifications for IP blocks, coordinating with power delivery team, maximizing die-per-reticle/good-die-per-wafer, RDL routing knowledge, and package integration before tape-out. **Qualifications:** - 12+ years of experience after a Bachelor or Master of Engineering degree in Electrical/Electronic/VLSI Engineering or related field. - Led multiple SOCs as SOC Floorplan lead, expertise in design planning, die estimation, knowledge of clocking, high-speed design signal routing, industry protocols, IP architecture, library/memory/technology/submicron issues. - Strong teamwork, flexibility, ability to thrive in a dynamic environment. **Job Type:** Experienced Hire **Shift:** Shift 1 (India) **Primary Location:** India, Bangalore Intel Foundry is committed to transforming the global semiconductor industry by providing cutting-edge silicon process and packaging technology. Innovating under Moore's Law, fostering collaboration, and investing in geographically diverse manufacturing capacities. Intel Foundry enables the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, dedicated to customer success with full P&L responsibilities.,

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This will involve working on a variety of components including yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to bring cutting-edge products to the market. Collaboration with cross-functional teams is a key aspect of this role to ensure that solutions meet performance requirements. The ideal candidate should have a minimum of 4 to 6 years of work experience in ASIC RTL Design. Experience in Logic design, micro-architecture, and RTL coding is essential. Hands-on experience with the design and integration of complex multi clock domain blocks is a must. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, APB, clocking/reset/debug architecture are also required. Candidates should have experience in Multi Clock designs and Asynchronous interface. Familiarity with ASIC development tools like Lint, CDC, Design compiler, and Primetime is necessary. An understanding of Automotive System Designs, Functional Safety, Memory controller designs, and microprocessors would be advantageous. The role involves close collaboration with Design verification and validation teams for pre/post Silicon debug. Prior experience in Low power design is preferred. Additionally, expertise in Synthesis and a solid grasp of timing concepts for ASIC are must-haves for this position.,

You should be an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog. Your expertise should cover all aspects of the RTL design flow, including Specification/Microarchitecture definition, design and verification, Timing Analysis, DFT, and Implementation. You should also have experience in Integration, RTL signoff tools, UPF/Low power signoff, CDC/RDC, and Lint. Your domain knowledge should be strong in Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. As a highly motivated individual, you should be a self-starter with excellent interpersonal skills and the ability to work effectively in a team. Strong communication, critical thinking, and problem-solving skills are essential for this role. Preferred education for this position is any degree.,