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cyient
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Staff Engineer - Design Verification

Staff Engineer - Design Verification

cyient

8 - 15 years

8 - 15 Lacs

Bengaluru Karnataka India

Posted:1 month ago| Platform: Foundit logo

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Skills Required

Uvm Verification

Work Mode

On-site

Job Type

Full Time

Job Description

Roles and Responsibilities

8yrs yrs of Experience in developing TB & TB components for block level and full chip level verification.
Experience in creating Test plan, writing Test cases
Proficient in System Verilog Verilog
Proficient in writing Assertions
UVM based Methodology with strong understanding of OOPS concepts
Good knowledge of Digital Fundamentals Good knowledge of Scripting (Perl, Shell), C language
Familiar with different aspects of IP development: micro-architecture, RTL & TB implementation, Test plan, Functional coverage, Code coverage and regression
Strong Simulation & Debugging skills
Strong analytical skills with attention to detail
Excellent written & verbal communications skills.
Knowledge of protocols such as PCI-Express, Rapid IO, NVM Express, NAND,CXL and DDR/ LPDDR
Experience implementing directed and random test cases. Very good leadership skills.
You will be a key player in IP development forMemory/Wired-Interconnect/Networking/Mobile/ Video
Develop BFMs, Drivers, Monitors and Scoreboard for the test bench in System Verilog.

Mandatory skills

oExperience in leading team atleast 5 member team.

0 Strong hands-on Verification experience in AMBA protocols

oStrong hands-on UVM, Assertions, RAL. Testbench flow.

oExperience intestbenche development using UVM.

oStrong hands-on experience in testbench run automation using make, c-shell or perl scripts

Good to have PMIC experience.

Skills Required

UVM, System Verilog, Verification

Location

Bengaluru, India

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