STA Engineer

• 5+ years of related work experience.


• You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity.


• You will collaborate effectively with cross-functional teams, communicate complex timing data clearly.


• Responsibilities will include: Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.


• Check timing for unconstrained endpoints, no clock, etc.


• Your role may include SDC validation, CDC delay check, and SDC flow development.


• Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.

Minimum Qualifications

• Bachelor s degree in electrical or computer engineering (or other equivalent field) with


• Experience with block/full chip SDC development in test modes (scan shift, scan capture, atpg capture modes).


• Expertise in Static Timing Analysis and prior working experience with STA tools like PrimeTime.


• Programming skills in at least 2 or more of the following languages: Perl, TCL, Python, Makefile, or other relative scripting languages.


• Preferred Qualifications


• Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.


• Prior working experience with SDC debugging & STA tools: Synopsys GCA/TCM/Primetime.


• Prior working experience with synthesis tools: Synopsys Fusion Compiler.


• Prior working experience with Tessent tool: DFT insertion in RTL.


• Strong communication skills and team player.