STA Engineer

• Define the architecture of Memory PHY IPs, its major blocks
• Responsible to develop the architecture and create specification for clocking, ASIC interface, pin-outs, bump-outs, floor plans, functionalities to support the protocol/system level requirements, Digital/Analog/Firmware Interface and partitions, calibration and other algorithm definition, test/debug logic etc
• Work with cross-functional teams and technical experts in various geographies to define and align scope of the IPs
• Support marketing on presales activities technically
• Be the interface to the customer in technical interactions, feasibility analysis, interoperability definitions and tracking
• Understand and disseminate applicable standards and its relevance in a given project to the team
• Provide definitions of scope and review the plans of verification team
• Work with the system engineering team for Silicon bring up and Characterization.

Skills/Qualifications:

• MS/M-Tech degree in electronics/VLSI and in exceptional cases B.E/B-Tech in electronics engineering with 10 years of relevant experience needed.
• The candidate should have prior experience of working on mixed signal designs, Signal Integrity analysis, Digital and Analog design, timing closure and simulation.
• Experience in designing memory systems such as DDR, LPDDR, GDDR, HBM
• Experience in architecture or micro-architecture development.
• Experience working with customers and cross-functional teams
• Experience working in leading RD and future technology development projects is desirable.
• The position requires good written verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.