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Sr Staff Engineer Design Verification/ VIP Verification Engineer

Sr Staff Engineer Design Verification/ VIP Verification Engineer

Synopsys

3 - 8 years

13 - 18 Lacs

bengaluru

Posted:4 hours ago| Platform:

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Skills Required

debugging system verilog verilog verification communication skills

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are looking for highly skilled and experienced R&D Engineering professionals to join our team at Synopsys (India) Private Limited. The ideal candidate will have a strong background in Design Verification/VIP Verification engineering with 5-10 years of experience.

Roles and Responsibility

Develop and implement verification environments for complex digital designs.
Collaborate with cross-functional teams to identify and prioritize verification requirements.
Design and develop testbenches, testcases, and simulation models for design verification.
Analyze and debug complex technical issues related to design verification.
Participate in code reviews and improve the overall quality of the verification environment.
Work closely with designers to ensure successful product delivery.

Job Requirements

Strong understanding of digital design principles and methodologies.
Experience with design verification tools such as Verilog, SystemVerilog, or UVM.
Excellent problem-solving skills and attention to detail.
Ability to work effectively in a team environment.
Strong communication and interpersonal skills.
Bachelor's degree in Computer Science, Electrical Engineering, or related field.

Disclaimer: This job description has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying.

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Sr Staff Engineer Design Verification/ VIP Verification Engineer