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Marvell Technology
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Sr. Principal Engineer, RTL Design { DDR4/5, LPDDR. HBM}

Sr. Principal Engineer, RTL Design { DDR4/5, LPDDR. HBM}

Marvell Technology

7 - 11 years

20 - 25 Lacs

Bengaluru

Posted:4 days ago| Platform:

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Skills Required

Semiconductor Prototype Simulation Architecture Packaging Perl System verilog Automotive Physical design Python

Work Mode

Work from Office

Job Type

Full Time

Job Description

About Marvell

Your Team, Your Impact

Data Centre Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up.

What You Can Expect

Define the memory sub system architecture, micro-architecture and register specification for highly complex SoCs. Drive and participate in specification writeup
Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers
Implement a specification using RTL coding techniques and best practices
Work with third party vendors to define customization requirements of third party IPs (controller, PHY, etc. )
Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff.
Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug
Help develop and/or evaluate design and verification methodologies and participate in improving existing ones
Collaborate with and provide guidance to the post silicon and software teams for prototype bring up and performance tuning
Provide mentorship to the more junior team members

What Were Looking For

Bachelor s degree in Computer Science, Electrical Engineering or related fields and 20+ years of related professional experience.
Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 18+ years of experience.
Experience in creating architectural, micro-architectural, and register specifications.
Verilog/System Verilog RTL coding with System Verilog assertions
Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up)
Expertise in high speed memory protocols (DDR4/5, LPDDR4/5X, HBM3)
Has worked on complex chips such as network processors, CPUs , GPUs , NOCs , Switches , Machine Learning SoCs etc. owning full chip, subsystem and block level architecture and design
Expertise in any of the following domains would be a big plus: networking, embedded systems architecture, computer architecture, machine learning accelerators
Experience with scripting in Perl/Python/Shell

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

#LI-CP1

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Sr. Principal Engineer, RTL Design { DDR4/5, LPDDR. HBM}