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Cadence
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SR Principal Design Engineer

SR Principal Design Engineer

8 - 14 years

|

25 - 30 Lacs

Posted:13 hours ago| Platform:

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Skills Required

rtl design usage vlsi debugging electronics system verilog pcie uvm electricals principal

Work Mode

Work from Office

Job Type

Full Time

Job Description

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
Exp- 8- 14 Yrs
RTL Design using Verilog is a must.
System Verilog experience and experience with UVM based environment usage / debugging is required.
PCIe experience is a must.

CXL/PXC experience desired.

.

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