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SR Principal Design Engineer

8 - 14 years

0 Lacs

bengaluru karnataka india

Posted:1 day ago| Platform: Foundit logo

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Skills Required

rtl design using verilog cxl uvm pxc

Work Mode

On-site

Job Type

Full Time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
  • Exp- 8- 14 Yrs
  • RTL Design using Verilog is a must.
  • System Verilog experience and experience with UVM based environment usage / debugging is required.
  • PCIe experience is a must.

CXL/PXC experience desired.

We're doing work that matters. Help us solve what others can't.

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SR Principal Design Engineer

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Salary: Not disclosed

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Cadence Design Systems (India) Pvt Ltd

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