Sr Principal Design Engineer

You will be a part of the DDR Memory Controller IP development team as an RTL Design Engineer at Cadence. Your responsibilities will include designing and supporting the RTL of the DDR Memory Controller solution, encompassing all leading DDR memory protocols such as DDR4/LPDDR4. You will work on the existing RTL, incorporate new features, ensure clean customer configurations in verification regressions, support customers, and ensure the design adheres to LINT and CDC design guidelines. Your qualifications should include a BE/B.Tech/ME/M.Tech degree in Electrical/Electronics/VLSI with experience as a design and verification engineer, focusing on RTL design and development. Proficiency in Verilog for RTL design is a must, along with experience in System Verilog and UVM-based environment usage/debugging. Knowledge of AXI3/4 is desired, and experience with DDR Memory controller and protocols is highly preferable. Previous experience in RTL design and implementation of complex protocols, particularly in IP development teams, would be advantageous. Cadence is a company that values hiring and nurturing leaders and innovators who aim to make a significant impact in the technology sector. Join us in our mission to tackle challenges that others find impossible to solve.,