Sr Principal Design Engineer

As a RTL Design Engineer for DDR Memory Controller IP development team at Cadence, your primary responsibility will be to design and support the RTL of the DDR Memory Controller solution. This entails supporting all leading DDR memory protocols including DDR4/LPDDR4. You will collaborate on working with the existing RTL, incorporating new features, ensuring customer configurations are clean during verification regressions, providing customer support, and ensuring the design adheres to LINT and CDC design guidelines. To qualify for this role, you should hold a BE/B.Tech/ME/M.Tech in Electrical/Electronics/VLSI and possess significant experience as a design and verification engineer, with a focus on RTL design and development. Proficiency in RTL Design using Verilog is essential, while experience with System Verilog and familiarity with UVM based environment usage/debugging are also required. AXI3/4 experience is desired, and prior exposure to DDR Memory controller and protocol is highly desirable. Having prior experience in RTL design and implementation of complex protocols, as well as in IP development teams, would be advantageous. Join us at Cadence, where we hire and develop leaders and innovators who strive to make a significant impact on the world of technology. Together, let's tackle challenges that others cannot solve.,