Sr Principal Design Engineer Cadence Design Systems

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a RTL Design Engineer for DDR Memory Controller IP development team at Cadence, your primary responsibility will be to design and support the RTL of the DDR Memory Controller solution. This entails supporting all leading DDR memory protocols including DDR4/LPDDR4. You will collaborate on working with the existing RTL, incorporating new features, ensuring customer configurations are clean during verification regressions, providing customer support, and ensuring the design adheres to LINT and CDC design guidelines. To qualify for this role, you should hold a BE/B.Tech/ME/M.Tech in Electrical/Electronics/VLSI and possess significant experience as a design and verification engineer, with a fo...

Posted 1 month ago

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Sr Principal Design Engineer Cadence

5.0 - 9.0 years

0 Lacs

pune, maharashtra

On-site

As a RTL Design Engineer for DDR Memory Controller IP development team at Cadence, your primary responsibility will be to design and support the RTL of the DDR Memory Controller solution. You will be working with the existing RTL, adding new features, and ensuring that all leading DDR memory protocols, including DDR4/LPDDR4, are supported. Your tasks will also involve ensuring customer configurations are clean as part of verification regressions, providing customer support, and ensuring the design meets LINT and CDC design guidelines. To qualify for this position, you should have a BE/B.Tech/ME/M.Tech degree in Electrical/Electronics/VLSI and proven experience as a design and verification en...

Posted 1 month ago

Apply

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