Sr Principal Design Engineer

As a RTL Design Engineer for DDR Memory Controller IP development team at Cadence, your primary responsibility will be to design and support the RTL of the DDR Memory Controller solution. You will be working with the existing RTL, adding new features, and ensuring that all leading DDR memory protocols, including DDR4/LPDDR4, are supported. Your tasks will also involve ensuring customer configurations are clean as part of verification regressions, providing customer support, and ensuring the design meets LINT and CDC design guidelines. To qualify for this position, you should have a BE/B.Tech/ME/M.Tech degree in Electrical/Electronics/VLSI and proven experience as a design and verification engineer, with a significant focus on RTL design and development. Proficiency in RTL Design using Verilog is essential, and familiarity with System Verilog and experience in using/debugging in a UVM based environment are required. AXI3/4 experience is preferred, and prior experience with DDR Memory controller and protocols is highly advantageous. Additionally, having prior experience in RTL design and implementation of complex protocols and working in IP development teams will be beneficial for this role. At Cadence, we are committed to making an impact on the world of technology by hiring and developing leaders and innovators like you. Join us in our mission to solve challenges that others can't and be part of a team that is dedicated to work that matters.,