4 - 11 years
0 - 19 Lacs
Posted:16 hours ago|
Platform:
On-site
Full Time
Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities
Must have worked in at least 1 Full Chip tape outs.
Must be hands-on technical expert.
Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling)
Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks)
Experience in Low power and high-performance designs.
Be able manage junior team members.
Should be able to comprehend architecture, architectural limitations from Physical Design perspective, schedule, and volume of the task and personnel requirement
Tessolve Semiconductor Private Limited
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