Sr. Design Engineer 1

About Us

Key Responsibilities

• Develop and implement DFT architectures for complex SoC/ASIC designs.
• Own and execute DFT insertion, ATPG pattern generation, and fault grading.
• Work on MBIST insertion, pattern development, and memory diagnostics.
• Collaborate with RTL, Verification, and Physical Design teams to ensure DFT compatibility and design closure.
• Support silicon bring-up and production test teams for debug and pattern validation.
• Drive improvements in DFT methodology and flow automation.
  

Required Skills

• Strong hands-on experience in DFT techniques: Scan, Boundary Scan, MBIST, LBIST, ATPG.
• Exposure to industry-standard DFT tools like Synopsys (TetraMAX/DFT Compiler/TestMax), Mentor Tessent or equivalent.
• Good knowledge of Verilog/VHDL and scripting languages (TCL, Perl, Python, Shell).
• Experience in gate-level simulations and debug of DFT patterns.
• Familiarity with STA and physical-aware DFT considerations is an added advantage.
  

Preferred Qualifications

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI-related stream.
• Experience working on full-chip DFT architecture and hierarchical DFT flow.
• Good communication and team collaboration skills.