Sr DFT Engineers and Managers - Complex SOC Solutions Assured Justice

5.0 - 9.0 years

18 - 42 Lacs

Bengaluru

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Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Health insurance

Posted 4 months ago

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DFT Engineer X-pert Matters Solutions

3.0 - 8.0 years

5 - 15 Lacs

Hyderabad

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Position: DFT Engineer (ASIC) Experience: 2+ Years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies f...

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Dft Engineer HCLTech

2.0 - 7.0 years

6 - 15 Lacs

Hyderabad, Chennai, Bengaluru

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Role & responsibilities DFT Engineer Must-Have: •Tools: Synopsys DFT Compiler, Tessent, Mentor TestKompress, Tetramax, Fastscan •Techniques: •Scan Insertion (ATPG) •Boundary Scan (JTAG) •MBIST, LBIST •Compression techniques •Stuck-at, Transition fault models •Simulation and validation of test vectors •DFT signoff and coverage reports •STA constraint generation for test modes Nice-to-Haves: •Tapeout experience •Knowledge of low-power test techniques •Integration of DFT at SoC level Common Green Flags Across Roles: •Product or IP ownership •Clear mention of project responsibilities (not just team contribution) •Mention of tapeouts or silicon-proven designs •Stable employment history (avoiding ...

Posted 5 months ago

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Senior Dft Engineer Cyient

4.0 - 8.0 years

15 - 30 Lacs

Hyderabad, Bengaluru

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About the Role Senior DFT Engineer (4 - 8 Years) | Hyderabad / Bangalore, India Are you passionate about making complex SoCs more testable, robust, and production-ready? As a Senior DFT Engineer , youll play a hands-on role in implementing critical DFT features that ensure silicon success across next-generation ASICs. You will work alongside experienced leads on advanced nodes (14nm and below), contribute to DFT flow development, and implement key test strategies such as scan compression, MBIST, and JTAG. This is your chance to grow into a technical specialist while playing a central role in the silicon lifecyclefrom RTL to tape-out. Key Responsibilities Support DFT architecture implementati...

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