Sr DFT Engineers and Managers - Complex SOC Solutions Assured Justice

5.0 - 9.0 years

18 - 42 Lacs

Bengaluru

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Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Health insurance

Posted 4 weeks ago

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DFT Engineer X-pert Matters Solutions

3.0 - 8.0 years

5 - 15 Lacs

Hyderabad

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Position: DFT Engineer (ASIC) Experience: 2+ Years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies for scan-based testing, MBIST, and boundary scan. Collaborate with RTL and physical design teams to ensure seamless DFT integration. Perform fault simulations , analyze test results, and drive improvements in test efficiency. Optimize DFT architectures for low-power, high-performance, and manufacturability . Support silicon bring-up and debug of test patterns on actual hardware. Work closely with foundries and test teams to ensure smooth production testing. Keep up to date with the latest DFT methodologies, trends, and innovations. Required Skills & Qualifications: 4+ years of experience in DFT implementation for ASIC designs. Proficiency in Synopsys EDA tools for test implementation and validation. Solid understanding of digital design, scan insertion, ATPG, and BIST . Experience with fault modeling, test coverage analysis, and debugging . Strong scripting skills in Python, Perl, or TCL for automation. Ability to work in a multi-disciplinary team and communicate technical concepts effectively. Preferred Qualifications: Experience with Post-Silicon Debug and ATE Testing . Knowledge of Verilog/VHDL and simulation tools . Familiarity with industry-standard DFT flows and methodologies .

Posted 1 month ago

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Dft Engineer HCLTech

2.0 - 7.0 years

6 - 15 Lacs

Hyderabad, Chennai, Bengaluru

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Role & responsibilities DFT Engineer Must-Have: •Tools: Synopsys DFT Compiler, Tessent, Mentor TestKompress, Tetramax, Fastscan •Techniques: •Scan Insertion (ATPG) •Boundary Scan (JTAG) •MBIST, LBIST •Compression techniques •Stuck-at, Transition fault models •Simulation and validation of test vectors •DFT signoff and coverage reports •STA constraint generation for test modes Nice-to-Haves: •Tapeout experience •Knowledge of low-power test techniques •Integration of DFT at SoC level Common Green Flags Across Roles: •Product or IP ownership •Clear mention of project responsibilities (not just team contribution) •Mention of tapeouts or silicon-proven designs •Stable employment history (avoiding frequent jumps unless justified) •Notice period 90 days •Clarity in resume: tools, technology nodes, project domains

Posted 2 months ago

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Senior Dft Engineer Cyient

4.0 - 8.0 years

15 - 30 Lacs

Hyderabad, Bengaluru

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About the Role Senior DFT Engineer (4 - 8 Years) | Hyderabad / Bangalore, India Are you passionate about making complex SoCs more testable, robust, and production-ready? As a Senior DFT Engineer , youll play a hands-on role in implementing critical DFT features that ensure silicon success across next-generation ASICs. You will work alongside experienced leads on advanced nodes (14nm and below), contribute to DFT flow development, and implement key test strategies such as scan compression, MBIST, and JTAG. This is your chance to grow into a technical specialist while playing a central role in the silicon lifecyclefrom RTL to tape-out. Key Responsibilities Support DFT architecture implementation and feature insertion for complex SoCs. Implement Scan Insertion , ATPG , Compression , MBIST , and Boundary Scan (JTAG) . Work with Mentor Graphics, Synopsys , or Cadence DFT tools for flow execution and verification. Generate and validate test vectors , support simulation, and ensure fault coverage goals. Assist with DFT verification , timing closure support , and pre-silicon checks . Collaborate with RTL, PD, and STA teams during integration and tape-out phases. Automate DFT flows using Tcl , Perl , or other scripting tools to improve efficiency. Contribute to post-silicon bring-up and production test debugging , where applicable. Work under the guidance of technical leads while also mentoring junior team members when needed. Required Skills & Qualifications Bachelor’s or Master’s degree in Electronics , Electrical Engineering , or a related discipline. 4–8 years of hands-on DFT experience in SoC/ASIC environments. Practical knowledge of: Scan/Compression Insertion and ATPG MBIST architectures and memory BIST flows Boundary Scan (JTAG / IEEE 1149.x) Exposure to silicon bring-up or production test is a strong advantage. Scripting experience using Tcl, Perl , or similar languages. Strong debugging, documentation, and collaboration skills. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Posted 2 months ago

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