2 Testmax Jobs

ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Who You Are You are an ASIC Design for Test Hardware Engineer with 10+ years of related work experience with a broad mix of technologies. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Skills: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post silicon validation using DFT patterns.

We are seeking a passionate and dynamic Lead Engineer Design for Test (DFT) to join our team. If you have extensive expertise in ATPG, SCAN, JTAG, and MBIST, and are eager to lead and mentor a talented team, this is the perfect opportunity for you! Key Responsibilities Lead and guide a team of engineers in the implementation of advanced DFT methodologies. Architect, implement, and validate DFT techniques, including ATPG, SCAN, JTAG, and MBIST, ensuring efficient and scalable design solutions. Collaborate closely with design, verification, and backend teams to deliver high-quality silicon solutions. Drive design reviews, debug issues, and ensure successful tape-out. Optimize and innovate DFT strategies for cutting-edge semiconductor designs. Required Skills and Experience 9+ years of experience in Design for Test (DFT) implementation and methodologies. Strong expertise in ATPG, SCAN, JTAG, MBIST , or at least one DFT technique with hands-on experience. Experience with industry-standard DFT tools such as Synopsys Tetramax, Mentor Tessent, Cadence Modus, or similar tools. Proven ability to debug DFT-related issues in pre-silicon and post-silicon environments. Excellent communication and leadership skills to lead and mentor a team. Proactive and adaptable with a problem-solving mindset. Preferred Qualifications Experience in SOC-level DFT implementation. Familiarity with RTL design and verification methodologies. Knowledge of silicon bring-up and testing processes. Why Join Us? Best Salary in the Market for the right candidate. Attractive bonus plan to reward your contributions. Be part of a fast-growing, innovative team driving next-generation semiconductor solutions. Opportunities to lead and shape projects with cutting-edge technology. A supportive and collaborative work environment that values your expertise and contributions. How to Apply? Please submit your application through prabhu.p@acldigital.com . For any queries, feel free to reach out me