End-to-end
Signal Integrity (SI) and Power Integrity (PI) simulations
across feasibility, pre-layout, and post-layout stages
Strong experience with
high-speed interfaces
: PCIe Gen 5/6/7, DDR5/DDR6, LPDDR5/6, HBM, DIMMs
Expertise in
multi-gigabit serial link simulations
(32G / 64G / 112G / 224 Gbps)
Hands-on experience with
SI/PI EDA tools
such as Ansys HFSS/SIwave, Cadence Sigrity, ADS, HyperLynx, HSPICE
Ability to correlate
simulation results with lab measurements

Electrical validation and compliance testing using
high-speed scopes, TDR, VNA
Experience working with
global cross-functional teams
Strong documentation and communication skills
Prior exposure to
manufacturing and NPI support

Perform
SI/PI simulations
at feasibility, pre-layout, and post-layout phases
Define and deliver
SI/PI constraints, stack-up guidelines, and layout rules
Conduct
channel simulations
for high-speed serial links and memory interfaces
Work closely with
HW design, PCB layout, NPI, and manufacturing vendors
Characterize interfaces and validate simulation results against
bench measurements
Prepare and execute
SI/PI checklists
across product development stages
Support
design reviews, risk mitigation, and silicon bring-up activities

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