Silicon Micro-architecture and RTL Lead

Role Overview: In this role, you will work to shape the future of AI/ML hardware acceleration, specifically focusing on driving cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You will be part of a team that develops custom silicon solutions to push boundaries and contribute to innovative products loved by millions worldwide. Your expertise in design and verification will be utilized to verify complex digital designs, with a particular emphasis on TPU architecture and its integration within AI/ML-driven systems. Additionally, as part of the team developing ASICs for data center traffic efficiency improvement, you will collaborate with cross-functional teams to deliver high-quality designs for next-generation data center accelerators. Key Responsibilities: - Drive development of Complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization. - Own micro-architecture and implementation of IPs and subsystems. - Collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications. - Lead design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. - Identify and drive Power, Performance, and Area improvements for the domains owned. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL). - Experience in micro-architecture and design IPs and Subsystems. - Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). - Experience with scripting languages (e.g., Python or Perl) is preferred. - Experience in SoC designs and integration flows is a plus. - Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies is desirable. - Familiarity with high performance and low power design techniques will be beneficial.,