Senior Staff ASIC Digital Design Engineer

Seeking a highly motivated and innovative Senior digital design engineer with knowledge of ASIC development flow. As a Senior Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes.

Responsibilities

• Lead the RTL synthesis and constraints generation/validation for MCU SoCs, ensuring they meet performance, power, and area specifications
• Develop and implement innovative implementation methodologies and tools to enhance productivity and design quality
• Be the bridge between Backend and Frontend teams to reconcile on hand-off and timing issues
• Conduct thorough design reviews and provide constructive feedback to peers and junior engineers
• Collaborate with cross-functional teams to not only resolve collateral issues but also to improve the overall PPA
• Support Low Power Implementation
• Support formality checks

Preferred Experience

• Experience in owning RTL synthesis and constraints for complex IPs/SS/SoC
• Experience in owning or supporting STA at full-chip level
• Exposure to latest methodologies in constraints generation, promotion/demotion and validation
• Familiarity with Low Power Implementation flows

Required and Preferred Qualifications

Required:

• Bachelors degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs
• BSEE degree and 12+ years of experience in IC design, or MSEE (or PhD) with 9+ years of experience and with a proven track record of delivering high-quality designs
• Experience with industry-standard EDA tools for synthesis, constraints validation and static timing analysis
• Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies
• Ability to mentor and guide junior engineers in IC design best practices and methodologies
• Scripting experience in Shell, Perl, Python and TCL is a plus
• Good communication skills for interacting between different design groups cross functional groups are required

Preferred:

• Experience with low-power design techniques and methodologies
• Familiarity with SoC design and integration

• Some level of understanding of DFT flows and steps
• Exposure to Automotive SoC designs