Senior Signal Integrity Engineer

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. The Power & Signal Integrity Group (PSIG) resides in the CHS (Central Hardware Systems) unit of Qualcomm Technologies, Inc., a leader in wireless communication technology. Engineers in the Power & Signal Integrity Group work with the various business units across Qualcomm to help bring leading edge mobile, AR\VR, IoT, Automotive and various others products to market. The candidate will work in a team-oriented environment with cross functional leads to provide electrical design expertise in the areas of signal integrity and power integrity for the design of wireless products and development systems. The engineer will be located in Bangalore, India and will be closely working with the Product architects, Platform HW teams, IO\PHY, IC Packaging, and other teams. The candidate is expected to perform SI / PI analyses and provide guidance on signal and power integrity challenges. Working effectively across organizational boundaries is essential as is the effective documentation and presentation of results. The candidate is expected to work closely with an experienced SI engineer while applying established PSIG methodologies. The engineer will have the opportunity to influence the evolution of analysis methodologies. Responsibilities Perform various IO analyses using established methodologies, potentially from model extraction through simulation and reporting of conclusions. IO types include DDR memory interfaces and variety of serial interfaces. Analyze and provide design guidance for DIE floor plans, IC packages, PCB power distribution networks using established methodologies. Document, distribute, and present results at appropriate meetings. 2+ years of work experience in the following areas: Electromagnetic theory and transmission lines Basic signal and power integrity concepts Commercial 3D electromagnetic field solver Commercial SI or RF simulation and analysis tools SPICE transient simulation including use of IBIS models The following experience is a plus: DDR and LPDDR design and analysis High speed serial IO design and analysis, PCIE, USB, UFS, CSI/DSI/MIPI Power Integrity analysis SI/PI tools :Ansys HFSS/SIwave, Cadence/Sigrity, Keysight ADS, HSPICE Spreadsheets and similar productivity tools Mentor or Cadence board design tools Education Requirements: Minimum Bachelor degree in Electrical Engineering or related discipline, Master degree preferred