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Senior RTL Design engineers

3 - 7 years

0 Lacs

hyderabad telangana

Posted:1 day ago| Platform: Shine logo

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Skills Required

rtl verilog system verilog logic synthesis timing closure soc architecture ip development axi bus protocols hardware debug xilinx fpgas vivado tool flows micro architecture development

Work Mode

On-site

Job Type

Full Time

Job Description

As a Senior RTL Design Engineer with 3-5 years of experience, you will be based in Hyderabad. You will be required to demonstrate strong RTL (Verilog/System Verilog) skills with a focus on IP development. Your responsibilities will include verifying designs by creating simple testbenches, as well as possessing a solid foundation in logic synthesis and timing closure concepts. Additionally, you should have a good understanding of SoC architecture, AXI bus protocols, and hardware debug processes. Experience with Xilinx FPGAs, Vivado tool flows, and micro-architecture development will be considered a plus. If you meet the specified requirements and are interested in this opportunity, please submit your updated resume to janagaradha.n@acldigital.com.,

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