2.0 - 6.0 years

3 - 7 Lacs

bengaluru, karnataka, india

On-site

ASIC Engineer Design Responsibilities Architecture exploration Micro-architecture development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, Power Optimization Soft and hard IP identification, selection and integration Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power Minimum Qualifications At least 7+ years of silicon development experience Track record of first-pass success in ASIC Development Experience with Verilog or System Verilog Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs, O...

Posted 10 hours ago

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