Senior Physical Design Engineer

As a Physical Design Engineer, you will be responsible for top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. You should have experience working on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias. In this role, you will provide technical guidance and mentoring to Physical Design Engineers and interface with front-end ASIC teams to resolve issues related to low power design techniques. Your responsibilities will also include timing closure on DDR2/DDR3/PCIE interfaces, ensuring excellent communication skills, and possessing a strong background in ASIC Physical Design encompassing Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. You should have extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools, expertise in scripting languages such as PERL, TCL, strong Physical Verification skill set, and proficiency in Static Timing Analysis in Primetime or Primetime-SI. In addition to technical responsibilities, you should have good written and oral communication skills, the ability to clearly document plans, and the capability to interface with different teams and prioritize work based on project needs. Qualifications: - Experience: 5 to 8 Years Location: - Hyderabad,