Senior IP Design Verification Engineer - NOC IP

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company.

What you ll be doing:

• You will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.

• Understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

• Coming up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.

• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.

• Work on advanced verification methodologies like SV/UVM.

• Perform functional coverage driven verification closure.

• Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

What we need to see:

• B. Tech. / M. Tech. , or equivalent experience.

• 5+ years of relevant experience.

• Experience in verification of complex IPs/units and sub-systems.

• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.

• Expertise in Verilog.

• Knowledge in SystemVerilog or similar HVL / UVM or VMM.

Ways to stand out from the crowd:

• Experience in memory subsystem or network interconnect IP verification.

• Debugging and analytical skills with sound scripting knowledge.

• Good communication and excellent team player.

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